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Fujitsu MPA3017AT, MPA3043AT, MPA3052AT, MPA3026AT, MPA3035AT Signal assignment on the connector

Models: MPA3017AT MPA3035AT MPA3026AT MPA3052AT MPA3043AT

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5.1.2Signal assignment on the connector

Table 5.1 shows the signal assignment on the interface connector.

Table 5.1 Signal assignment on the interface connector

Pin No.	Signal	Pin No.	Signal

1	RESET–	2	GND
3	DATA7	4	DATA8
5	DATA6	6	DATA9
7	DATA5	8	DATA10
9	DATA4	10	DATA11
11	DATA3	12	DATA12
13	DATA2	14	DATA13
15	DATA1	16	DATA14
17	DATA0	18	DATA15
19	GND	20	(KEY)
21	DMARQ	22	GND
23	IOW–, STOP	24	GND
25	IOR–, HDMARDY–, HSTROBE	26	GND
27	IORDY, DDMARDY–, DSTROBE	28	CSEL
29	DMACK–	30	GND
31	INTRQ	32	IOCS16–
33	DA1	34	PDIAG–
35	DA0	36	DA2
37	CS0–	38	CS1–
39	DASP–	40	GND

[signal]	[I/O]	[Description]
RESET–	I	Reset signal from the host. This signal is low active and is asserted
		for a minimum of 25 μs during power on.
DATA 0-15	I/O	Sixteen-bit bi-directional data bus between the host and the device.
		These signals are used for data transfer
IOW–, STOP	I	IOW– is the strobe signal asserted by the host to write device
		registers or the data port.
		IOW– shall be negated by the host prior to initiation of an Ultra
		DMA burst. STOP shall be negated by the host before data is
		transferred in an Ultra DMA burst. Assertion of STOP by the host
		during an Ultra DMA burst signals the termination of the Ultra DMA
		burst.

C141-E034-02EN

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Fujitsu MPA3017AT, MPA3043AT, MPA3052AT Signal assignment on the connector, 1 Signal assignment on the interface connector

Contents

PRODUCT MANUAL MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT DISK DRIVESC141-E034-02EN Revised contents REVISION RECORDEdition Date publishedDEVICE CONFIGURATION INSTALLATION CONDITIONSPREFACE ChapterConventions for Alert Messages LIABILITY EXCEPTION C141-E034-02ENCONTENTS CHAPTERCHAPTER CHAPTERCHAPTER CHAPTERCommand block registers Host CommandsCommand code and parameters Command descriptionsPower save mode Power commandsData buffer configuration 6.3.1FIGURES Protocol for command abort WRITE SECTORS command protocolProtocol for the command execution without data transfer Multiword DMA data transfer timing modeTABLES 1.1 Features 1.2 Device Specifications 1.3 Power Requirements 1.4 Environmental Specifications 1.5 Acoustic Noise1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.1 Features 1.1.1 Functions and performance1.1.2 Adaptability 1.1.3 Interface6 Write cache 5 Error correction and retry by ECCC141-E034-02EN 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 Specifications1.2.2 Model and product number 1.3 Power RequirementsTable 1.2 Model names and product numbers Table 1.3 Current and power dissipation Figure 1.1 Current fluctuation Typ. at +5V when power is turned on 1.4 Environmental Specifications Environmental specificationsTable 1.5 Acoustic noise specification 1.5 Acoustic Noise1.6 Shock and Vibration Table 1.6 Shock and vibration specification1.7 Reliability 1.8 Error Rate 1.9 Media DefectsCHAPTER 2 DEVICE CONFIGURATION 2.1 Device Configuration 2.2 System Configuration2.1 Device Configuration Figure 2.1 Disk drive outerview1 Disk MPA3017AT 1 disk MPA3026AT 2 disks MPA3035AT 2 disksMPA3043AT 3 disks MPA3052AT 3 disks 2 Head C141-E034-02ENFigure 2.2 Configuration of disk media heads Figure 2.3 1 drive system configuration 2.2 System Configuration 2.2.1 ATA interface2.2.2 1 drive connection Figure 2.4 2 drives configuration 2.2.3 2 drives connectionHost HA Host adaptor AT bus Host interface3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings CHAPTER 3 INSTALLATION CONDITIONS3.1 Dimensions Figure 3.1 Dimensions C141-E034-02EN3.2 Mounting Figure 3.2 OrientationFigure 3.4 Mounting frame structure Figure 3.3 Limitation of side-mountingcabinet Figure 3.5 Surface temperature measurement points Table 3.1 Surface temperature measurement points and standard valuesService area Mounting screw hole3.3 Cable Connections 3.3.1 Device connector Figure 3.7 Connector locations∙ Power supply connector CN1 ∙ ATA interface connector CN1 Power supply connector CN1 Mode Setting Pins ATA interface connector3.3.2 Cable connector specifications Table 3.2 Cable connector specifications3.3.3 Device connection Figure 3.8 Cable connections3.3.4 Power supply connector CN1 Figure 3.9 Power supply connector pins CN1 3.4 Jumper Settings3.4.1 Location of setting jumpers Figure 3.10 Jumper locationFigure 3.11 Factory default setting 3.4.3 Jumper configuration 3.4.2 Factory default settingFigure 3.12 Jumper setting of master or slave device Figure 3.14 Example 1 of Cable Select Figure 3.13 Jumper setting of Cable SelectFigure 3.15 Example 2 of Cable Select 3 Special setting 1 SP1 a Default modeb Special mode Master Device4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration 4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/Write circuitCHAPTER 4 THEORY OF DEVICE OPERATION 4.7 Servo Control4.2.2 Head Figure 4.1 Head structure4.2.4 Actuator 4.2.3 Spindle4.2.5 Air filter 4.3 Circuit Configuration Figure 4.2 MPA30xxAT Block diagram C141-E034-02EN4.4 Power-on Sequence Figure 4.3 Power-on operation sequence 4.5.1 Self-calibration contents 4.5 Self-calibrationTable 4.1 Self-calibration execution timechart 4.5.3 Command processing during self-calibration4.6 Read/write Circuit 4.6.1 Read/write preamplifier PreAMP4.6.2 Write circuit Table 4.2 Write precompensation algorithmFigure 4.4 Read/write circuit block diagram C141-E034-02ENFigure 4.5 Frequency characteristic of programmable filter 4.6.3 Read circuitFigure 4.6 PR4 signal transfer C141-E034-02EN4.6.4 Time base generator circuit Table 4.3 Write clock frequency and transfer rate of each zone 4.7 Servo ControlFigure 4.7 Block diagram of servo control circuit 4.7.1 Servo control circuitFigure 4.8 Physical sector servo configuration on disk surface c. Seek to specified cylinderDrives the VCM to position the head to the specified cylinder d. Calibration5 Power amplifier 2 Servo burst capture circuit3 A/D converter ADC 4 D/A converter DAC4.7.3 Servo frame format 4.7.2 Data-surface servo formatFigure 4.9 Servo frame format 4.7.4 Actuator motor control 4.7.5 Spindle motor control 3 Stable rotation mode 2 Acceleration modeC141-E034-02EN 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Ultra DMA Feature Set 5.6 TimingCHAPTER INTERFACE5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 Interface signals5.1.2 Signal assignment on the connector Table 5.1 Signal assignment on the interface connectorsignal This signal is used for DMA transfer between the host system and the 5.2 Logical Interface 5.2.1 I/O registersI/O registers 5.2.2 Command block registers Diagnostic code X01 No Error Detected X02 HDC Register Compare Error X03 Data Buffer Compare Error X05 ROM Sum Check Error3 Features register X1F1 X80 Device 1 slave device Failed6 Cylinder Low register X1F4 9 Status register X1F7 DRDYCORR C141-E034-02ENAlways 10 Command register X1F7C141-E034-02EN 5.3 Host Commands 5.2.3 Control block registers5.3.1 Command code and parameters Table 5.3 Command code and parameters 1 ofTable 5.3 Command code and parameters 2 of 5.3.2 Command descriptions Transfer sector countAt command issuance I/O registers setting contents 1 READ SECTORS X20 or1F7 HCM 1F6 HDHAt command completion I/O registers contents to be read Error information1F7 HST Status informationFigure 5.2 Execution example of READ MULTIPLE command ∙ The data transfer starts at the timing of DMARQ signal assertion In LBA mode1 Single word DMA transfer mode 2 Multiword DMA transfer modeAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents 1F7 HSTAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents 1F7 HSTAt command completion I/O registers contents to be read Error information1F7 HST Status informationAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information ∙ The data transfer starts at the timing of DMARQ signal assertion1 Single word DMA transfer mode 2 Multiword DMA transfer mode3 Ultra DMA transfer mode At command issuance I/O registers setting contentsAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information This command can be issued in the LBA modeAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents At command completion I/O registers contents to be readIn LBA mode At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error InformationAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 1F7HCMTable 5.4 Information to be read by IDENTIFY DEVICE command 1 of C141-E034-02ENTable 5.4 Information to be read by IDENTIFY DEVICE command 2 of Table 5.4 Information to be read by IDENTIFY DEVICE command 3 of At command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 14 SET FEATURES XEFTable 5.5 Features register values and settable modes X‘AA’PIO default transfer mode PIO flow control transfer modeX‘08’ Mode X‘09’ ModeAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 1F7HCMTable 5.6 Diagnostic code At command issuance I/O registers setting contents At command completion I/O registers contents to be readDiagnostic code 1 This register indicates X‘00’ in the LBA mode 17 FORMAT TRACKAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information This command is operated under the following conditionsAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents At command completion I/O registers contents to be readPoint of timer Disable of timerAt command issuance I/O registers setting contents Period of timerAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents At command completion I/O registers contents to be readAt command issuance I/O registers setting contents Period of timerAt command completion I/O registers contents to be read Error informationAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information This command is the only way to make the device enter the sleep modeAt command completion I/O registers contents to be read Error information27 CHECK POWER MODE X98 or XE5 The host checks the power mode of the device with this commandAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 1F7 HCMTable 5.7 Features Register values subcommands and functions Features ResisterAt command issuance I-O registers setting contents SubcommandAt command completion I-O registers setting contents Error informationTable 5.8 Format of device attribute value data Format of insurance failure threshold value data Power-on time Number of power-on-power-off timesWrite error rate ∙ Attribute ID The attribute ID is defined as follows∙ Raw attribute value Raw attributes data is retained ∙ Failure prediction capability flagBits 2 to 15 Reserved bits ∙ Check sum ∙ Insurance failure threshold5.3.3 Error posting Table 5.10 Command code and parametersINDF ABRT5.4 Command Protocol 5.4.1 Data transferring commands from device to hostFigure 5.3 Read Sectors command protocol Figure 5.4 Protocol for command abort 5.4.2 Data transferring commands from host to deviceFigure 5.5 WRITE SECTORS command protocol 5.4.3 Commands without data transfer Figure 5.6 Protocol for the command execution without data transfer5.4.4 Other commands 5.4.5 DMA data transfer commandsFigure 5.7 Normal DMA data transfer 5.5 Ultra DMA feature set 5.5.1 Overview 5.5.3 Ultra DMA data in commands 5.5.2 Phases of operation5.5.3.1 Initiating an Ultra DMA data in burst 5.5.3.3 Pausing an Ultra DMA data in burst 5.5.3.2 The data in transfer5.5.3.4 Terminating an Ultra DMA data in burst b Host terminating an Ultra DMA data in burst C141-E034-02EN5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst5.5.4.3 Pausing an Ultra DMA data out burst 5.5.4.2 The data out transfer5.5.4.4 Terminating an Ultra DMA data out burst b Device terminating an Ultra DMA data out burst C141-E034-02EN5.5.5 Ultra DMA CRC rules Table 5.11 Recommended series termination for Ultra DMA 5.5.6 Series termination required for Ultra DMAFigure 5.8 Ultra DMA termination with pull-up or pull-down 5.6 Timing 5.6.1 PIO data transfer C141-E034-02ENFigure 5.9 PIO data transfer timing 5.6.2 Single word DMA data transfer Figure 5.10 Single word DMA data transfer timingFigure 5.11 Multiword DMA data transfer timing mode 5.6.3 Multiword data transfer5.6.4.1 Initiating an Ultra DMA data in burst 5.6.4 Ultra DMA data transferFigure 5.12 Initiating an Ultra DMA data in burst 5.6.4.2 Ultra DMA data burst timing requirements Table 5.12 Ultra DMA data burst timing requirementstZIORDY tIORDYZtACK 5.6.4.3 Sustained Ultra DMA data in burst Figure 5.13 Sustained Ultra DMA data in burst5.6.4.4 Host pausing an Ultra DMA data in burst Figure 5.14 Host pausing an Ultra DMA data in burst5.6.4.5 Device terminating an Ultra DMA data in burst Figure 5.15 Device terminating an Ultra DMA data in burst5.6.4.6 Host terminating an Ultra DMA data in burst Figure 5.16 Host terminating an Ultra DMA data in burst5.6.4.7 Initiating an Ultra DMA data out burst Figure 5.17 Initiating an Ultra DMA data out burst5.6.4.8 Sustained Ultra DMA data out burst Figure 5.18 Sustained Ultra DMA data out burst5.6.4.9 Device pausing an Ultra DMA data out burst Figure 5.19 Device pausing an Ultra DMA data out burst5.6.4.10 Host terminating an Ultra DMA data out burst Figure 5.20 Host terminating an Ultra DMA data out burst5.6.4.11 Device terminating an Ultra DMA data in burst Figure 5.21 Device terminating an Ultra DMA data out burst5.6.5 Power-on and reset Figure 5.22 Power-on Reset Timing6.1 Device Response to the Reset 6.2 Address Translation 6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache6.6 Write Cache 6.1 Device Response to the Reset OPERATIONS6.1.1 Response to power-on Figure 6.1 Response to power-on6.1.2 Response to hardware reset Figure 6.2 Response to hardware resetFigure 6.3 Response to software reset 6.1.3 Response to software resetMaster device 6.1.4 Response to diagnostic command Figure 6.4 Response to diagnostic commandDefault parameters 6.2.1 Default parameters6.2 Address Translation Figure 6.5 Address translation example in CHS mode 6.2.2 Logical addressFigure 6.6 Address translation example in LBA mode 6.3 Power Save 6.3.1 Power save mode1 Active mode A device enters the active mode under the following conditions∙ Power-on sequence is completed ∙ A command other than power commands is issued6.3.2 Power commands 6.4 Defect Management6.4.1 Spare area 6.4.2 Alternating defective sectorsFigure 6.7 Sector slip processing DefectiveFigure 6.8 Alternate cylinder assignment Figure 6.9 Data buffer configuration 6.5.1 Data buffer configuration6.5 Read-Ahead Cache 6.5.2 Caching operation 6.5.3 Usage of read segment 4 Following shows the cache enabled data for next read command Cache enabled dataHAP Segment only for read DAP Stores the read-requested data upto this pointa. Sequential command just after non-sequential command 3 Sequential readMis-hit data Empty dataHAP Read-ahead data DAP Last LBA Start LBA b. Sequential hit HAP Completion of transferring requested dataRead-ahead data Hit datac. Non-sequential read command just after sequential read command HAP Read-ahead data DAP4 Finally, the cache data in the buffer is as follows Read-ahead data Start LBALast position at previous read command DAP Last position at previous read command3 The cache data for next read command is as follows Cache data HAP set to hit position for data transferDAP stopped 3 The cache data for next read command is as follows Partially hit dataLack data Requested data to be transferred6.6 Write Cache When the write cache function is enabled, the transferred data from the host by the WRITE SECTORS is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function Page 61-2-411-8603 FUJITSU LIMITED Reader Comment Form