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Fujitsu MPA3017AT, MPA3043AT, MPA3052AT, MPA3026AT, MPA3035AT Control block registers, Host Commands

Models: MPA3017AT MPA3035AT MPA3026AT MPA3052AT MPA3043AT

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5.2.3Control block registers

(1)Alternate Status register (X'3F6')

The Alternate Status register contains the same information as the Status register of the command block register.

The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit	1	Bit 0

BSY	DRDY	DF	DSC	DRQ	CORR	0		ERR

(2)Device Control register (X'3F6')

The Device Control register contains device interrupt and software reset.

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit	0

X	X	X	X	X	SRST	nIEN	0

-Bit 2: SRST is the host software reset bit. When this bit is set, the device is held reset state. When two device are daisy chained on the interface, setting this bit resets both device simultaneously.

The slave device is not required to execute the DASP- handshake.

-Bit 1: nIEN bit enables an interrupt (INTRQ signal) from the device to the host. When this bit is 0 and the device is selected, an interruption (INTRQ signal) can be enabled through a tri-state buffer. When this bit is 1 or the device is not selected, the INTRQ signal is in the high-impedance state.

5.3Host Commands

The host system issues a command to the device by writing necessary parameters in related registers in the command block and writing a command code in the Command register.

The device can accept the command when the BSY bit is 0 (the device is not in the busy status).

The host system can halt the uncompleted command execution only at execution of hardware or software reset.

When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host system writes to the command register, the correct device operation is not guaranteed.

C141-E034-02EN

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Fujitsu MPA3017AT, MPA3043AT, MPA3052AT, MPA3026AT, MPA3035AT manual Control block registers, Host Commands

Contents

C141-E034-02EN MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT DISK DRIVESPRODUCT MANUAL Edition Revised contentsREVISION RECORD Date publishedPREFACE DEVICE CONFIGURATIONINSTALLATION CONDITIONS ChapterConventions for Alert Messages LIABILITY EXCEPTION C141-E034-02ENCHAPTER CONTENTSCHAPTER CHAPTERCHAPTER CHAPTERCommand code and parameters Command block registersHost Commands Command descriptionsData buffer configuration Power save modePower commands 6.3.1FIGURES Protocol for the command execution without data transfer Protocol for command abortWRITE SECTORS command protocol Multiword DMA data transfer timing modeTABLES 1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate 1.1 Features 1.2 Device Specifications 1.3 Power Requirements1.4 Environmental Specifications 1.5 Acoustic Noise 1.1 Features 1.1.1 Functions and performance1.1.2 Adaptability 1.1.3 InterfaceC141-E034-02EN 5 Error correction and retry by ECC6 Write cache 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 SpecificationsTable 1.2 Model names and product numbers 1.3 Power Requirements1.2.2 Model and product number Table 1.3 Current and power dissipation Figure 1.1 Current fluctuation Typ. at +5V when power is turned on Table 1.5 Acoustic noise specification 1.4 Environmental SpecificationsEnvironmental specifications 1.5 Acoustic Noise1.7 Reliability Table 1.6 Shock and vibration specification1.6 Shock and Vibration 1.8 Error Rate 1.9 Media Defects2.1 Device Configuration CHAPTER 2 DEVICE CONFIGURATION2.1 Device Configuration 2.2 System Configuration Figure 2.1 Disk drive outerviewMPA3043AT 3 disks MPA3052AT 3 disks 2 Head 1 DiskMPA3017AT 1 disk MPA3026AT 2 disks MPA3035AT 2 disks C141-E034-02ENFigure 2.2 Configuration of disk media heads 2.2.2 1 drive connection 2.2 System Configuration 2.2.1 ATA interfaceFigure 2.3 1 drive system configuration Host Figure 2.4 2 drives configuration2.2.3 2 drives connection HA Host adaptor AT bus Host interface3.1 Dimensions CHAPTER 3 INSTALLATION CONDITIONS3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings Figure 3.1 Dimensions C141-E034-02EN3.2 Mounting Figure 3.2 Orientationcabinet Figure 3.3 Limitation of side-mountingFigure 3.4 Mounting frame structure Figure 3.5 Surface temperature measurement points Table 3.1 Surface temperature measurement points and standard valuesService area Mounting screw hole∙ Power supply connector CN1 ∙ ATA interface connector CN1 3.3 Cable Connections 3.3.1 Device connectorFigure 3.7 Connector locations Power supply connector CN1 Mode Setting Pins ATA interface connector3.3.3 Device connection 3.3.2 Cable connector specificationsTable 3.2 Cable connector specifications Figure 3.8 Cable connections3.4.1 Location of setting jumpers 3.3.4 Power supply connector CN1Figure 3.9 Power supply connector pins CN1 3.4 Jumper Settings Figure 3.10 Jumper locationFigure 3.12 Jumper setting of master or slave device 3.4.2 Factory default settingFigure 3.11 Factory default setting 3.4.3 Jumper configuration Figure 3.15 Example 2 of Cable Select Figure 3.13 Jumper setting of Cable SelectFigure 3.14 Example 1 of Cable Select b Special mode 3 Special setting 1 SP1a Default mode Master DeviceCHAPTER 4 THEORY OF DEVICE OPERATION 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/Write circuit 4.7 Servo Control4.2.2 Head Figure 4.1 Head structure4.2.5 Air filter 4.2.3 Spindle4.2.4 Actuator 4.3 Circuit Configuration Figure 4.2 MPA30xxAT Block diagram C141-E034-02EN4.4 Power-on Sequence Figure 4.3 Power-on operation sequence 4.5.1 Self-calibration contents 4.5 Self-calibrationTable 4.1 Self-calibration execution timechart 4.5.3 Command processing during self-calibration4.6.2 Write circuit 4.6 Read/write Circuit4.6.1 Read/write preamplifier PreAMP Table 4.2 Write precompensation algorithmFigure 4.4 Read/write circuit block diagram C141-E034-02ENFigure 4.5 Frequency characteristic of programmable filter 4.6.3 Read circuitFigure 4.6 PR4 signal transfer C141-E034-02EN4.6.4 Time base generator circuit Table 4.3 Write clock frequency and transfer rate of each zone 4.7 Servo ControlFigure 4.7 Block diagram of servo control circuit 4.7.1 Servo control circuitDrives the VCM to position the head to the specified cylinder Figure 4.8 Physical sector servo configuration on disk surfacec. Seek to specified cylinder d. Calibration3 A/D converter ADC 5 Power amplifier2 Servo burst capture circuit 4 D/A converter DACFigure 4.9 Servo frame format 4.7.2 Data-surface servo format4.7.3 Servo frame format 4.7.4 Actuator motor control 4.7.5 Spindle motor control C141-E034-02EN 2 Acceleration mode3 Stable rotation mode CHAPTER 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands5.4 Command Protocol 5.5 Ultra DMA Feature Set 5.6 Timing INTERFACE5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 Interface signals5.1.2 Signal assignment on the connector Table 5.1 Signal assignment on the interface connectorsignal This signal is used for DMA transfer between the host system and the 5.2 Logical Interface 5.2.1 I/O registersI/O registers 5.2.2 Command block registers 3 Features register X1F1 Diagnostic code X01 No Error Detected X02 HDC Register Compare ErrorX03 Data Buffer Compare Error X05 ROM Sum Check Error X80 Device 1 slave device Failed6 Cylinder Low register X1F4 CORR 9 Status register X1F7DRDY C141-E034-02ENC141-E034-02EN 10 Command register X1F7Always 5.3 Host Commands 5.2.3 Control block registers5.3.1 Command code and parameters Table 5.3 Command code and parameters 1 ofTable 5.3 Command code and parameters 2 of 5.3.2 Command descriptions Transfer sector count1F7 HCM At command issuance I/O registers setting contents1 READ SECTORS X20 or 1F6 HDH1F7 HST At command completion I/O registers contents to be readError information Status informationFigure 5.2 Execution example of READ MULTIPLE command 1 Single word DMA transfer mode ∙ The data transfer starts at the timing of DMARQ signal assertionIn LBA mode 2 Multiword DMA transfer modeAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 1F7 HSTAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information 1F7 HST1F7 HST At command completion I/O registers contents to be readError information Status informationError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read ∙ The data transfer starts at the timing of DMARQ signal assertion3 Ultra DMA transfer mode 1 Single word DMA transfer mode2 Multiword DMA transfer mode At command issuance I/O registers setting contentsError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read This command can be issued in the LBA modeAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information At command completion I/O registers contents to be readAt command completion I/O registers contents to be read In LBA modeAt command issuance I/O registers setting contents Error InformationError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 1F7HCMTable 5.4 Information to be read by IDENTIFY DEVICE command 1 of C141-E034-02ENTable 5.4 Information to be read by IDENTIFY DEVICE command 2 of Table 5.4 Information to be read by IDENTIFY DEVICE command 3 of Error information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 14 SET FEATURES XEFTable 5.5 Features register values and settable modes X‘AA’X‘08’ Mode PIO default transfer modePIO flow control transfer mode X‘09’ ModeError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 1F7HCMTable 5.6 Diagnostic code Diagnostic code At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 1 This register indicates X‘00’ in the LBA mode 17 FORMAT TRACKError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read This command is operated under the following conditionsError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information At command completion I/O registers contents to be readAt command issuance I/O registers setting contents Point of timerDisable of timer Period of timerAt command issuance I/O registers setting contents At command completion I/O registers contents to be readError information At command completion I/O registers contents to be readAt command completion I/O registers contents to be read At command issuance I/O registers setting contentsPeriod of timer Error informationError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read This command is the only way to make the device enter the sleep mode27 CHECK POWER MODE X98 or XE5 At command completion I/O registers contents to be readError information The host checks the power mode of the device with this commandError information At command issuance I/O registers setting contentsAt command completion I/O registers contents to be read 1F7 HCMTable 5.7 Features Register values subcommands and functions Features ResisterAt command completion I-O registers setting contents At command issuance I-O registers setting contentsSubcommand Error informationTable 5.8 Format of device attribute value data Format of insurance failure threshold value data Write error rate Power-on timeNumber of power-on-power-off times ∙ Attribute ID The attribute ID is defined as followsBits 2 to 15 Reserved bits ∙ Check sum ∙ Raw attribute value Raw attributes data is retained∙ Failure prediction capability flag ∙ Insurance failure thresholdINDF 5.3.3 Error postingTable 5.10 Command code and parameters ABRT5.4 Command Protocol 5.4.1 Data transferring commands from device to hostFigure 5.3 Read Sectors command protocol Figure 5.4 Protocol for command abort 5.4.2 Data transferring commands from host to deviceFigure 5.5 WRITE SECTORS command protocol 5.4.3 Commands without data transfer Figure 5.6 Protocol for the command execution without data transfer5.4.4 Other commands 5.4.5 DMA data transfer commandsFigure 5.7 Normal DMA data transfer 5.5 Ultra DMA feature set 5.5.1 Overview 5.5.3.1 Initiating an Ultra DMA data in burst 5.5.2 Phases of operation5.5.3 Ultra DMA data in commands 5.5.3.3 Pausing an Ultra DMA data in burst 5.5.3.2 The data in transfer5.5.3.4 Terminating an Ultra DMA data in burst b Host terminating an Ultra DMA data in burst C141-E034-02EN5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst5.5.4.3 Pausing an Ultra DMA data out burst 5.5.4.2 The data out transfer5.5.4.4 Terminating an Ultra DMA data out burst b Device terminating an Ultra DMA data out burst C141-E034-02EN5.5.5 Ultra DMA CRC rules Figure 5.8 Ultra DMA termination with pull-up or pull-down 5.5.6 Series termination required for Ultra DMATable 5.11 Recommended series termination for Ultra DMA 5.6 Timing 5.6.1 PIO data transfer C141-E034-02ENFigure 5.9 PIO data transfer timing 5.6.2 Single word DMA data transfer Figure 5.10 Single word DMA data transfer timingFigure 5.11 Multiword DMA data transfer timing mode 5.6.3 Multiword data transferFigure 5.12 Initiating an Ultra DMA data in burst 5.6.4 Ultra DMA data transfer5.6.4.1 Initiating an Ultra DMA data in burst 5.6.4.2 Ultra DMA data burst timing requirements Table 5.12 Ultra DMA data burst timing requirementstACK tIORDYZtZIORDY 5.6.4.3 Sustained Ultra DMA data in burst Figure 5.13 Sustained Ultra DMA data in burst5.6.4.4 Host pausing an Ultra DMA data in burst Figure 5.14 Host pausing an Ultra DMA data in burst5.6.4.5 Device terminating an Ultra DMA data in burst Figure 5.15 Device terminating an Ultra DMA data in burst5.6.4.6 Host terminating an Ultra DMA data in burst Figure 5.16 Host terminating an Ultra DMA data in burst5.6.4.7 Initiating an Ultra DMA data out burst Figure 5.17 Initiating an Ultra DMA data out burst5.6.4.8 Sustained Ultra DMA data out burst Figure 5.18 Sustained Ultra DMA data out burst5.6.4.9 Device pausing an Ultra DMA data out burst Figure 5.19 Device pausing an Ultra DMA data out burst5.6.4.10 Host terminating an Ultra DMA data out burst Figure 5.20 Host terminating an Ultra DMA data out burst5.6.4.11 Device terminating an Ultra DMA data in burst Figure 5.21 Device terminating an Ultra DMA data out burst5.6.5 Power-on and reset Figure 5.22 Power-on Reset Timing6.6 Write Cache 6.1 Device Response to the Reset 6.1 Device Response to the Reset 6.2 Address Translation6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache OPERATIONS6.1.1 Response to power-on Figure 6.1 Response to power-on6.1.2 Response to hardware reset Figure 6.2 Response to hardware resetMaster device 6.1.3 Response to software resetFigure 6.3 Response to software reset 6.1.4 Response to diagnostic command Figure 6.4 Response to diagnostic command6.2 Address Translation 6.2.1 Default parametersDefault parameters Figure 6.5 Address translation example in CHS mode 6.2.2 Logical addressFigure 6.6 Address translation example in LBA mode 6.3 Power Save 6.3.1 Power save mode∙ Power-on sequence is completed 1 Active modeA device enters the active mode under the following conditions ∙ A command other than power commands is issued6.3.2 Power commands 6.4 Defect ManagementFigure 6.7 Sector slip processing 6.4.1 Spare area6.4.2 Alternating defective sectors DefectiveFigure 6.8 Alternate cylinder assignment 6.5 Read-Ahead Cache 6.5.1 Data buffer configurationFigure 6.9 Data buffer configuration 6.5.2 Caching operation 6.5.3 Usage of read segment HAP Segment only for read DAP 4 Following shows the cache enabled data for next read commandCache enabled data Stores the read-requested data upto this pointMis-hit data a. Sequential command just after non-sequential command3 Sequential read Empty dataRead-ahead data HAP Read-ahead data DAP Last LBA Start LBA b. Sequential hitHAP Completion of transferring requested data Hit data4 Finally, the cache data in the buffer is as follows Read-ahead data c. Non-sequential read command just after sequential read commandHAP Read-ahead data DAP Start LBA3 The cache data for next read command is as follows Cache data Last position at previous read commandDAP Last position at previous read command HAP set to hit position for data transferLack data DAP stopped 3 The cache data for next read command is as followsPartially hit data Requested data to be transferred6.6 Write Cache When the write cache function is enabled, the transferred data from the host by the WRITE SECTORS is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function Page 61-2-411-8603 FUJITSU LIMITED Reader Comment Form