Fujitsu MPA3052AT, MPA3043AT, MPA3026AT manual Single word DMA data transfer, Dmarq Dmack DIOR-/DIOW

5.6.2Single word DMA data transfer

Figure 5.10 show the single word DMA data transfer timing between the device and the host system.

				t0
DMARQ
		tC
DMACK-
		tI		tD	tJ
DIOR-/DIOW-
Write data
DD0-DD15
				tG	tH
Read data
DD0-DD15
			tE		tF
Symbol		Timing parameter					Min.	Max.	Unit
t0	Cycle time					240		—	ns
tC	Delay time from DMACK assertion to DMARQ negation						—	80	ns
tD	Pulse width of DIOR-/DIOW-					120		—	ns
tE	Data setup time for DIOR-						—	60	ns
tF	Data hold time for DIOR-					5		—	ns
tG	Data setup time for DIOW-					35		—	ns
tH	Data hold time for DIOW-					20		—	ns
tI	DMACK setup time for DIOR-/DIOW-					0		—	ns
tJ	DMACK hold time for DIOR-/DIOW-					0		—	ns

Figure 5.10 Single word DMA data transfer timing

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