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MPA3026AT manual Chapter, Physical Interface 5.2 Logical Interface 5.3 Host Commands
Models:
MPA3017AT
MPA3035AT
MPA3026AT
MPA3052AT
MPA3043AT
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Specifications
Install
Dimension
Data buffer configuration
Device Response to the Reset
Response to diagnostic command
Command block registers
Error Rate
Point of timer
6 PR4 signal transfer
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CHAPTER 5
INTERFACE
5.1 Physical Interface
5.2 Logical Interface
5.3 Host Commands
5.4 Command Protocol
5.5 Ultra DMA Feature Set
5.6 Timing
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5 - 1
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Contents
C141-E034-02EN
MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT DISK DRIVES
PRODUCT MANUAL
Edition
Revised contents
REVISION RECORD
Date published
PREFACE
DEVICE CONFIGURATION
INSTALLATION CONDITIONS
Chapter
Conventions for Alert Messages
LIABILITY EXCEPTION
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CHAPTER
CONTENTS
CHAPTER
CHAPTER
CHAPTER
CHAPTER
Command code and parameters
Command block registers
Host Commands
Command descriptions
Data buffer configuration
Power save mode
Power commands
6.3.1
FIGURES
Protocol for the command execution without data transfer
Protocol for command abort
WRITE SECTORS command protocol
Host pausing an Ultra DMA data in burst
TABLES
1.6 Shock and Vibration 1.7 Reliability 1.8 Error Rate
1.1 Features 1.2 Device Specifications 1.3 Power Requirements
1.4 Environmental Specifications 1.5 Acoustic Noise
1.1 Features 1.1.1 Functions and performance
1.1.2 Adaptability
1.1.3 Interface
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5 Error correction and retry by ECC
6 Write cache
1.2 Device Specifications 1.2.1 Specifications summary
Table 1.1 Specifications
Table 1.2 Model names and product numbers
1.3 Power Requirements
1.2.2 Model and product number
Table 1.3 Current and power dissipation
Figure 1.1 Current fluctuation Typ. at +5V when power is turned on
Table 1.5 Acoustic noise specification
1.4 Environmental Specifications
Environmental specifications
1.5 Acoustic Noise
1.7 Reliability
Table 1.6 Shock and vibration specification
1.6 Shock and Vibration
1.8 Error Rate
1.9 Media Defects
2.1 Device Configuration
CHAPTER 2 DEVICE CONFIGURATION
2.1 Device Configuration 2.2 System Configuration
Figure 2.1 Disk drive outerview
MPA3043AT 3 disks MPA3052AT 3 disks 2 Head
1 Disk
MPA3017AT 1 disk MPA3026AT 2 disks MPA3035AT 2 disks
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Figure 2.2 Configuration of disk media heads
2.2.2 1 drive connection
2.2 System Configuration 2.2.1 ATA interface
Figure 2.3 1 drive system configuration
Host
Figure 2.4 2 drives configuration
2.2.3 2 drives connection
HA Host adaptor AT bus Host interface
3.1 Dimensions
CHAPTER 3 INSTALLATION CONDITIONS
3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings
Figure 3.1 Dimensions
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3.2 Mounting
Figure 3.2 Orientation
cabinet
Figure 3.3 Limitation of side-mounting
Figure 3.4 Mounting frame structure
Figure 3.5 Surface temperature measurement points
Table 3.1 Surface temperature measurement points and standard values
Service area
Mounting screw hole
∙ Power supply connector CN1 ∙ ATA interface connector CN1
3.3 Cable Connections 3.3.1 Device connector
Figure 3.7 Connector locations
Power supply connector CN1 Mode Setting Pins ATA interface connector
3.3.3 Device connection
3.3.2 Cable connector specifications
Table 3.2 Cable connector specifications
Figure 3.8 Cable connections
3.4.1 Location of setting jumpers
3.3.4 Power supply connector CN1
Figure 3.9 Power supply connector pins CN1 3.4 Jumper Settings
Figure 3.10 Jumper location
Figure 3.12 Jumper setting of master or slave device
3.4.2 Factory default setting
Figure 3.11 Factory default setting 3.4.3 Jumper configuration
Figure 3.15 Example 2 of Cable Select
Figure 3.13 Jumper setting of Cable Select
Figure 3.14 Example 1 of Cable Select
Master Device
3 Special setting 1 SP1
a Default mode
Slave Device
CHAPTER 4 THEORY OF DEVICE OPERATION
4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration
4.4 Power-on sequence 4.5 Self-calibration 4.6 Read/Write circuit
4.7 Servo Control
4.2.2 Head
Figure 4.1 Head structure
4.2.5 Air filter
4.2.3 Spindle
4.2.4 Actuator
4.3 Circuit Configuration
Figure 4.2 MPA30xxAT Block diagram
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4.4 Power-on Sequence
Figure 4.3 Power-on operation sequence
4.5.1 Self-calibration contents
4.5 Self-calibration
Table 4.1 Self-calibration execution timechart
4.5.3 Command processing during self-calibration
4.6.2 Write circuit
4.6 Read/write Circuit
4.6.1 Read/write preamplifier PreAMP
Table 4.2 Write precompensation algorithm
Figure 4.4 Read/write circuit block diagram
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Figure 4.5 Frequency characteristic of programmable filter
4.6.3 Read circuit
Figure 4.6 PR4 signal transfer
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4.6.4 Time base generator circuit
Table 4.3 Write clock frequency and transfer rate of each zone
4.7 Servo Control
Figure 4.7 Block diagram of servo control circuit
4.7.1 Servo control circuit
Drives the VCM to position the head to the specified cylinder
Figure 4.8 Physical sector servo configuration on disk surface
c. Seek to specified cylinder
d. Calibration
3 A/D converter ADC
5 Power amplifier
2 Servo burst capture circuit
4 D/A converter DAC
Figure 4.9 Servo frame format
4.7.2 Data-surface servo format
4.7.3 Servo frame format
4.7.4 Actuator motor control
4.7.5 Spindle motor control
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2 Acceleration mode
3 Stable rotation mode
CHAPTER
5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands
5.4 Command Protocol 5.5 Ultra DMA Feature Set 5.6 Timing
INTERFACE
5.1 Physical Interface 5.1.1 Interface signals
Figure 5.1 Interface signals
5.1.2 Signal assignment on the connector
Table 5.1 Signal assignment on the interface connector
signal
This signal is used for DMA transfer between the host system and the
5.2 Logical Interface
5.2.1 I/O registers
I/O registers
5.2.2 Command block registers
3 Features register X1F1
Diagnostic code X01 No Error Detected X02 HDC Register Compare Error
X03 Data Buffer Compare Error X05 ROM Sum Check Error
X80 Device 1 slave device Failed
6 Cylinder Low register X1F4
CORR
9 Status register X1F7
DRDY
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10 Command register X1F7
Always
5.3 Host Commands
5.2.3 Control block registers
5.3.1 Command code and parameters
Table 5.3 Command code and parameters 1 of
Table 5.3 Command code and parameters 2 of
5.3.2 Command descriptions
Transfer sector count
1F7 HCM
At command issuance I/O registers setting contents
1 READ SECTORS X20 or
1F6 HDH
1F7 HST
At command completion I/O registers contents to be read
Error information
Status information
Figure 5.2 Execution example of READ MULTIPLE command
3 READ DMA XC8 or XC9
∙ The data transfer starts at the timing of DMARQ signal assertion
At command issuance I/O registers setting contents
In LBA mode
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
Error information
1F7 HST
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
Error information
1F7 HST
1F7 HST
At command completion I/O registers contents to be read
Error information
Status information
Error information
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
∙ The data transfer starts at the timing of DMARQ signal assertion
Error information
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
1 Single word DMA transfer mode
Error information
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
This command can be issued in the LBA mode
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
Error information
At command completion I/O registers contents to be read
Error Information
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
11 INITIALIZE DEVICE PARAMETERS
Error information
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
1F7HCM
Table 5.4 Information to be read by IDENTIFY DEVICE command 1 of
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Table 5.4 Information to be read by IDENTIFY DEVICE command 2 of
Table 5.4 Information to be read by IDENTIFY DEVICE command 3 of
Error information
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
14 SET FEATURES XEF
Table 5.5 Features register values and settable modes
X‘AA’
X‘00’
PIO default transfer mode
00000
PIO flow control transfer mode
Error information
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
1F7HCM
Table 5.6 Diagnostic code
Diagnostic code
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
The READ LONG command supports only single sector operation
Error information
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
This command is operated under the following conditions
Error information
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
At command issuance I/O registers setting contents
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
Error information
At command completion I/O registers contents to be read
At command issuance I/O registers setting contents
Point of timer
Disable of timer
Period of timer
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
Error information
At command completion I/O registers contents to be read
At command completion I/O registers contents to be read
At command issuance I/O registers setting contents
Period of timer
Error information
Error information
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
This command is the only way to make the device enter the sleep mode
27 CHECK POWER MODE X98 or XE5
At command completion I/O registers contents to be read
Error information
The host checks the power mode of the device with this command
Error information
At command issuance I/O registers setting contents
At command completion I/O registers contents to be read
1F7 HCM
Table 5.7 Features Register values subcommands and functions
Features Resister
At command completion I-O registers setting contents
At command issuance I-O registers setting contents
Subcommand
Error information
Table 5.8 Format of device attribute value data
Format of insurance failure threshold value data
Write error rate
Power-on time
Number of power-on-power-off times
∙ Attribute ID The attribute ID is defined as follows
Bits 2 to 15 Reserved bits ∙ Check sum
∙ Raw attribute value Raw attributes data is retained
∙ Failure prediction capability flag
∙ Insurance failure threshold
INDF
5.3.3 Error posting
Table 5.10 Command code and parameters
ABRT
5.4 Command Protocol
5.4.1 Data transferring commands from device to host
Figure 5.3 Read Sectors command protocol
Figure 5.4 Protocol for command abort
5.4.2 Data transferring commands from host to device
Figure 5.5 WRITE SECTORS command protocol
5.4.3 Commands without data transfer
Figure 5.6 Protocol for the command execution without data transfer
5.4.4 Other commands
5.4.5 DMA data transfer commands
Figure 5.7 Normal DMA data transfer
5.5 Ultra DMA feature set 5.5.1 Overview
5.5.3.1 Initiating an Ultra DMA data in burst
5.5.2 Phases of operation
5.5.3 Ultra DMA data in commands
5.5.3.3 Pausing an Ultra DMA data in burst
5.5.3.2 The data in transfer
5.5.3.4 Terminating an Ultra DMA data in burst
b Host terminating an Ultra DMA data in burst
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5.5.4 Ultra DMA data out commands
5.5.4.1 Initiating an Ultra DMA data out burst
5.5.4.3 Pausing an Ultra DMA data out burst
5.5.4.2 The data out transfer
5.5.4.4 Terminating an Ultra DMA data out burst
b Device terminating an Ultra DMA data out burst
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5.5.5 Ultra DMA CRC rules
Figure 5.8 Ultra DMA termination with pull-up or pull-down
5.5.6 Series termination required for Ultra DMA
Table 5.11 Recommended series termination for Ultra DMA
5.6 Timing 5.6.1 PIO data transfer
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Figure 5.9 PIO data transfer timing
5.6.2 Single word DMA data transfer
Figure 5.10 Single word DMA data transfer timing
5.6.3 Multiword data transfer
Figure 5.11 Multiword DMA data transfer timing mode
Figure 5.12 Initiating an Ultra DMA data in burst
5.6.4 Ultra DMA data transfer
5.6.4.1 Initiating an Ultra DMA data in burst
5.6.4.2 Ultra DMA data burst timing requirements
Table 5.12 Ultra DMA data burst timing requirements
tACK
tIORDYZ
tZIORDY
5.6.4.3 Sustained Ultra DMA data in burst
Figure 5.13 Sustained Ultra DMA data in burst
5.6.4.4 Host pausing an Ultra DMA data in burst
Figure 5.14 Host pausing an Ultra DMA data in burst
5.6.4.5 Device terminating an Ultra DMA data in burst
Figure 5.15 Device terminating an Ultra DMA data in burst
5.6.4.6 Host terminating an Ultra DMA data in burst
Figure 5.16 Host terminating an Ultra DMA data in burst
5.6.4.7 Initiating an Ultra DMA data out burst
Figure 5.17 Initiating an Ultra DMA data out burst
5.6.4.8 Sustained Ultra DMA data out burst
Figure 5.18 Sustained Ultra DMA data out burst
5.6.4.9 Device pausing an Ultra DMA data out burst
Figure 5.19 Device pausing an Ultra DMA data out burst
5.6.4.10 Host terminating an Ultra DMA data out burst
Figure 5.20 Host terminating an Ultra DMA data out burst
5.6.4.11 Device terminating an Ultra DMA data in burst
Figure 5.21 Device terminating an Ultra DMA data out burst
5.6.5 Power-on and reset
Figure 5.22 Power-on Reset Timing
6.6 Write Cache 6.1 Device Response to the Reset
6.1 Device Response to the Reset 6.2 Address Translation
6.3 Power Save 6.4 Defect Management 6.5 Read-Ahead Cache
OPERATIONS
6.1.1 Response to power-on
Figure 6.1 Response to power-on
6.1.2 Response to hardware reset
Figure 6.2 Response to hardware reset
Master device
6.1.3 Response to software reset
Figure 6.3 Response to software reset
6.1.4 Response to diagnostic command
Figure 6.4 Response to diagnostic command
6.2 Address Translation
6.2.1 Default parameters
Default parameters
6.2.2 Logical address
Figure 6.5 Address translation example in CHS mode
Figure 6.6 Address translation example in LBA mode 6.3 Power Save
6.3.1 Power save mode
∙ Reset hardware or software 2 Idle mode
∙ Power-on sequence is completed
∙ A command other than power commands is issued
∙ After completion of power-on sequence
6.3.2 Power commands
6.4 Defect Management
Figure 6.7 Sector slip processing
6.4.1 Spare area
6.4.2 Alternating defective sectors
Defective
Figure 6.8 Alternate cylinder assignment
6.5 Read-Ahead Cache
6.5.1 Data buffer configuration
Figure 6.9 Data buffer configuration
6.5.2 Caching operation
6.5.3 Usage of read segment
HAP Segment only for read DAP
4 Following shows the cache enabled data for next read command
Cache enabled data
Stores the read-requested data upto this point
Mis-hit data
a. Sequential command just after non-sequential command
3 Sequential read
Empty data
Read-ahead data
HAP Read-ahead data DAP Last LBA Start LBA b. Sequential hit
HAP Completion of transferring requested data
Hit data
4 Finally, the cache data in the buffer is as follows Read-ahead data
c. Non-sequential read command just after sequential read command
HAP Read-ahead data DAP
Start LBA
3 The cache data for next read command is as follows Cache data
Last position at previous read command
DAP Last position at previous read command
HAP set to hit position for data transfer
Lack data
DAP stopped 3 The cache data for next read command is as follows
Partially hit data
Requested data to be transferred
6.6 Write Cache
When the write cache function is enabled, the transferred data from the host by the WRITE SECTORS is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. However an interrupt of abnormal end is not generated when a write automatic assignment succeeds. However, since the host may issue several write commands before the drive generates an interrupt of abnormal end, the host cannot recognize that the occurred error is for which command generally. Therefore, it is very hard to retry the unrecoverable write error for the host in the write cache operation generally. So, take care to use the write cache function
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