SPI Controller, Theory of Operation | Lantronix DSTni-EX specification

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Lantronix DSTni-EX manual Theory of Operation, SPI Background, DSTni SPI Controller

Contents

DSTni-EX User Guide Section FivePage Copyright & Trademark LantronixTechnical Support Master Distributor Warranty Contents 1 About This User Guide2 SPI Controller 3 I2C Controller List of Tables 5 CAN Controllers Table 3-17. Clock Control Register List of Figures 1 About This User Guide Intended Audience ConventionsNavigating Online Notes Notes are information requiring attention Organization 2 SPI Controller Theory of OperationSPI Background DSTni SPI Controller SPI Controller Register Summary Table 2-1. SPI Controller Register Summary SPI Controller Register Definitions SPIDATA RegisterRESET Table 2-2. SPIDATA Register CTL Register Interrupt Request EnablePhase Select Wire-O SPISTAT Register Table 2-6. SPISTAT RegisterTable 2-7. SPISTAT Register Definitions Interrupt Request SPISSEL Register Table 2-10. BCNT Bit SettingsSelectO Signal Table 2-8. SPISSEL Register DVDCNTRLO Register DVDCNTRHITable 2-11. DVDCNTRLO Register Table 2-12. DVDCNTRLO Register Definitions Features 3 I2C Controller Block Diagram I2C BackgroundFigure 3-1. DSTni I2C Controller Block Diagram I2C Controller Operating ModesMaster Transmit Mode Table 3-1. Master Transmit Status Codes CodeI2C State Microprocessor Response Servicing the Interrupt Table 3-2. Codes After Servicing Interrupts Master Transmit Transmitting Each Data Byte Table 3-3. Status Codes After Each Data Byte TransmitsAll Bytes Transmit Completely Master Receive Mode Table 3-4. Master Receive Status Codes Table 3-5. Codes After Servicing Interrupt Master Receive Receiving Each Data Byte Table 3-6. Codes After Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Bus Clock Considerations Bus Clock SpeedClock Synchronization Bus Arbitration Programmer’s Reference I2C Controller Register SummaryResetting the I2C Controller Table 3-7. I 2C Controller Register Summary I2C Controller Register Definitions Slave Address RegisterGeneral Call Address Enable Table 3-8. Slave Address Register Data Register Table 3-10. Data Register Control Register Table 3-12. Control RegisterTable 3-13. Control Register Definitions Extended Slave Address Status Register Table 3-14. Status Register Table 3-15. Status Register Definitions Table 3-16. Status CodesStatus Code Clock Control Register Table 3-17. Clock Control RegisterTable 3-18. Clock Control Register Definitions Software Reset Register Extended Slave Address RegisterTable 3-21. Software Reset Register Table 3-22. Software Reset Register Definitions 4 USB Controller USB Background USB InterruptUSB Core Serial Interface Engine USB Hardware/Software Interface Digital Phase Lock Loop LogicMicroprocessor Interface Buffer Descriptor Table Figure 4-1. Buffer Descriptor Table Rx vs. Tx as a Target Device or Host Table 4-1. USB Data Direction Addressing BDT EntriesTable 4-2. 16-Bit USB Address Table 4-3. 16-Bit USB Address Definitions Table 4-4. BDT Data Used by USB Controller and Microprocessor USB Controller Determines…Microprocessor Determines… Table 4-5. USB Buffer Descriptor Format Table 4-6. USB Buffer Descriptor Format Definitions BD OwnerDATA0/1 Transmit or Receive USB Ownership USB Transaction Figure 4-2. USB Token Transaction USB Register Summary Table 4-7. USB Register SummaryDedicated to host mode USB Register Definitions Interrupt Status RegisterTable 4-8. Interrupt Status Register Table 4-9. 16- Interrupt Status Register Definitions Enable/Disable USBRST Interrupt Sleep TimerError Condition USB Reset Error Register Table 4-10. Error Interrupt Status RegisterTable 4-11. 16- Error Interrupt Status Register Definitions Error interrupt with two functions Data Field Received Not 8 BitsCRC16 Failure PID check field failed Live USB Differential Receiver JSTATE Signal Live USB Single Ended Zero SignalTable 4-12. Status Register Table 4-13. Status Register Definitions USB Reset Signal Host Mode Enable valid for host mode onlyResume Signaling BDT PDD Reset Address Register Table 4-14. Address RegisterTable 4-15. 16- Address Register Definitions Frame Number Registers Table 4-16. Frame Number RegisterTable 4-17. Frame Number Register Definitions Frame Number Token Register Endpoint for Token Command Table 4-18. Token RegisterTable 4-19. Token Register Definitions Table 4-20. Valid PID Tokens Endpoint Control Registers Endpoint EnableTable 4-21. Endpoint Control Registers Table 4-22. Endpoint Control Register Definitions Host Mode Operation Table 4-23. Endpoint Control Register Definitions Sample Host Mode Operations Figure 3. Enable Host Mode and Configure a Target Device Figure 4. Full-Speed Bulk Data Transfers to a Target Device USB Pull-up/Pull-down Resistors Figure 4-5. Pull-up/Pull-down USB USB Interface Signals USB Output EnableHOST Mode Enable Clock CLK 5 CAN Controllers Arbitration and Error Checking CANBUS BackgroundData Exchanges and Communication CANBUS Speed and Length Table 5-1. Bit Rates for Different Cable Lengths CAN Register Summaries Register SummaryHex Offset Register Hex Offset Detailed CAN Register Map Table 5-4. Detailed CAN Register Map Acceptance Filter Enable Register Hex Offset Register CAN Register Definitions TX Message RegistersFigure 5-1. TX Message Routing Sending a Message Tx Message Registers Table 5-5. TxMessage0ID28Table 5-6. TxMessage0ID12 Table 5-7. TxMessage0Data Table 5-12. TxMessage0Ctrl Flags Table 5-13. TxMessage0 Register DefinitionsMessage Identifier for Both Standard and Extended Messages Message Data RX Message Registers Figure 5-2. RX Message Routing Rx Message Registers Table 5-14. RxMessageID28Table 5-15. Rx Message ID28 Register Definitions Table 5-16. RxMessageID12 Table 5-20. Rx Message Data Table 5-21. Rx Message Data 39 Register DefinitionsTable 5-22. Rx Message Data Table 5-23. Rx Message Data 23 Register Definitions Table 5-26. RxMessage RTR Table 5-27. Rx Message RTR Register DefinitionsTable 5-28. Rx Message Msg Flags Table 5-29. Rx Message Msg Flags Register Definitions Error Count and Status Registers Table 5-30. Tx/Rx Error CountTable 5-31. Tx\Rx Error Count Register Definitions Table 5-32. Error Status Table 5-34. Tx/Rx Message Level Register Table 5-35. Tx/Rx Message Level Register Definitionsrxlevel10 txlevel10 Interrupt Flags Note The reset value of this register’s bits is indeterminateCRC Error Format Error Interrupt Enable Registers Table 5-38. Interrupt Enable RegistersTable 5-39. Interrupt Enable Register Definitions Bus Off State − int2n group error interrupts CAN Operating Mode Table 5-40. Interrupt Enable RegistersTable 5-41. Interrupt Enable Register Definitions Overload Condition − int3n group diagnostic interrupts CAN Configuration Registers Configuration Bit RateFigure 5-3. CAN Operating Mode Table 5-42. Bit Rate Divisor Register Table 5-44. Configuration Register Table 5-45. Configuration Register DefinitionsOverwrite Last Message Cfgsjw Bit Time tseg1 +tseg2 + time quanta TQ Acceptance Filter and Acceptance Code Mask Table 5-46. Acceptance Filter Enable RegisterTable 5-47. Acceptance Filter Enable Register Definitions Table 5-48. Acceptance Mask 0 Register Table 5-50. Acceptance Mask Register ID Table 5-51. Acceptance Mask Register ID12 DefinitionsTable 5-52. Acceptance Mask Register Data D5556 Table 5-54. Acceptance Code Register Table 5-55. Acceptance Code Register DefinitionsTable 5-56. Acceptance Mask Register ID12 Table 5-57. Acceptance Mask Register ID12 Definitions CANbus Analysis Arbitration Lost Capture RegisterTable 5-60. Arbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register Definitions Error Capture Register Table 5-62. Error Capture RegisterTable 5-63. Error Capture Register Definitions Errorcode Table 5-65. Error Capture Register Definitions Frame Reference RegisterTable 5-64. Frame Reference Register Stuff Bit Inserted CAN Bus Interface Interface ConnectionsFigure 5-6. CAN Connector Figure 5-5. CAN Bus Interface Figure 5-7. Power for CAN +5CANGNDCAN +24V Figure 5-8. CAN Transceiver and Isolation Circuits 0.01uf