Receiving Each Data Byte
After receiving each data byte, the IFLG is set and one of three status codes in Table
When all bytes are received, set the STP bit by writing a 1 to it in the Control register. The I2C controller:
Transmits a STOP condition Clears the STP bit Returns to the idle state
| Table | |||
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Code | I2C State |
| Microprocessor Response | Next I2C Action |
50h | Data byte received, |
| Read DATA, clear IFLG, AAK=0 | Receive data byte, transmit not ACK |
| ACK transmitted |
| OR |
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| |
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| Read DATA, clear IFLG, AAK=1 | Receive data byte, transmit ACK |
58h | Data byte received, Not |
| Read DATA, set STA, clear IFLG | Transmit repeated START |
| ACK transmitted |
| OR |
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| |
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| Read DATA, set STP, clear IFLG | Transmit STOP |
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| OR |
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| Read DATA, set STA & STP, clear | Transmit STOP then START |
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| IFLG |
|
38h | Arbitration lost in not |
| Clear IFLG | Return to idle |
| ACK bit |
| OR |
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| |
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| Set STA, clear IFLG | Transmit START when bus free |
Slave Transmit Mode
In the slave transmit mode, a number of bytes are transmitted to a master receiver.
The I2C controller enters slave transmit mode when it receives its own slave address and a read bit after a START condition. The I2C controller then transmits an acknowledge bit and sets the IFLG bit in the Control register. The Status register contains the status code A8h.
Note: If the I2C controller has an extended slave address (signified by F0h - F7h in the Slave Address register), it transmits an acknowledge after receiving the first address byte, but does not generate an interrupt; the IFLG is not set and the status does not change. Only after receiving the second address byte does The I2C controller generate an interrupt and set the IFLG bit and status code as described above.
The I2C controller can also enter slave transmit mode directly from a master mode if arbitration is lost in master mode during address transmission, and both the slave address and read bit are received. The status code in the Status register is B0h.
After the I2C controller enters slave transmit mode:
1.The Data register loads the data byte to be transmitted, then IFLG clears.
2.The I2C controller transmits the byte.
3.The I2C controller receives or does not receive an acknowledge. If the I2C controller receives an acknowledge:
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