USB Background, USB Interrupt, USB Core | Lantronix DSTni-EX

Theory of Operation

USB Background

USB is a serial bus operating at 12 Mb/s. USB provides an expandable, hot-pluggable Plug- and-Play serial interface that ensures a standard, low-cost socket for adding external peripheral devices.

USB allows the connection of up to 127 devices. Devices suitable for USB range from simple input devices such as keyboards, mice, and joysticks, to advanced devices such as printers, scanners, storage devices, modems, and video-conferencing cameras.

Version 1.1 of the USB specification provides for peripheral speeds of up to 1.5 Mbps for low- speed devices and up to 12 Mbps for full-speed devices.

USB Interrupt

The DSTni USB interrupt is located at base input/output (I/O) of 9800h. It is logically ORed with external interrupt 3.

USB Core

The USB core has three functional blocks.

Serial Interface Engine (SIE)

Microprocessor Interface

Digital Phase-Locked Loop Logic

Serial Interface Engine

The USB Serial Interface Engine (USB SIE) has two major sections: Tx Logic and Rx Logic.

Tx Logic formats and transmits data packets that the microprocessor builds in memory. These packets are converted from a parallel-to-serial data stream. Tx Logic performs all the necessary USB data formatting, including:

NRZI encoding Bit-stuff

Cyclic Redundancy Check (CRC) computation Addition of SYNC field and EOP

The Rx Logic receives USB data and stores the packets in memory so the microprocessor can process them. Serial USB data converts to a byte-wide parallel data stream and is stored in system memory. The receive logic:

Decodes an NRZ USB serial data stream Performs bit-stuff removal

Performs CRC check, PID check, and other USB protocol-layer checks

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Lantronix DSTni-EX manual USB Background, USB Interrupt, USB Core, Theory of Operation, Serial Interface Engine

Contents

Section Five DSTni-EX User GuidePage Master Distributor Copyright & TrademarkLantronix Technical Support Warranty 3 I2C Controller Contents1 About This User Guide 2 SPI Controller 5 CAN Controllers List of Tables Table 3-17. Clock Control Register List of Figures 1 About This User Guide Notes Notes are information requiring attention Intended AudienceConventions Navigating Online Organization DSTni SPI Controller 2 SPI ControllerTheory of Operation SPI Background Table 2-1. SPI Controller Register Summary SPI Controller Register Summary Table 2-2. SPIDATA Register SPI Controller Register DefinitionsSPIDATA Register RESET Wire-O CTL RegisterInterrupt Request Enable Phase Select Interrupt Request SPISTAT RegisterTable 2-6. SPISTAT Register Table 2-7. SPISTAT Register Definitions Table 2-8. SPISSEL Register SPISSEL RegisterTable 2-10. BCNT Bit Settings SelectO Signal Table 2-12. DVDCNTRLO Register Definitions DVDCNTRLO RegisterDVDCNTRHI Table 2-11. DVDCNTRLO Register 3 I2C Controller Features Block Diagram I2C BackgroundFigure 3-1. DSTni I2C Controller Block Diagram I2C Controller Operating ModesMaster Transmit Mode Microprocessor Response Table 3-1. Master Transmit Status CodesCode I2C State Table 3-2. Codes After Servicing Interrupts Master Transmit Servicing the Interrupt Master Receive Mode Transmitting Each Data ByteTable 3-3. Status Codes After Each Data Byte Transmits All Bytes Transmit Completely Table 3-4. Master Receive Status Codes Table 3-5. Codes After Servicing Interrupt Master Receive Receiving Each Data Byte Table 3-6. Codes After Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Bus Arbitration Bus Clock ConsiderationsBus Clock Speed Clock Synchronization Table 3-7. I 2C Controller Register Summary Programmer’s ReferenceI2C Controller Register Summary Resetting the I2C Controller Table 3-8. Slave Address Register I2C Controller Register DefinitionsSlave Address Register General Call Address Enable Table 3-10. Data Register Data Register Extended Slave Address Control RegisterTable 3-12. Control Register Table 3-13. Control Register Definitions Table 3-14. Status Register Status Register Table 3-15. Status Register Definitions Table 3-16. Status CodesStatus Code Clock Control Register Table 3-17. Clock Control RegisterTable 3-18. Clock Control Register Definitions Table 3-22. Software Reset Register Definitions Software Reset RegisterExtended Slave Address Register Table 3-21. Software Reset Register 4 USB Controller Serial Interface Engine USB BackgroundUSB Interrupt USB Core Buffer Descriptor Table USB Hardware/Software InterfaceDigital Phase Lock Loop Logic Microprocessor Interface Rx vs. Tx as a Target Device or Host Figure 4-1. Buffer Descriptor Table Table 4-3. 16-Bit USB Address Definitions Table 4-1. USB Data DirectionAddressing BDT Entries Table 4-2. 16-Bit USB Address Table 4-5. USB Buffer Descriptor Format Table 4-4. BDT Data Used by USB Controller and MicroprocessorUSB Controller Determines… Microprocessor Determines… USB Ownership Table 4-6. USB Buffer Descriptor Format DefinitionsBD Owner DATA0/1 Transmit or Receive Figure 4-2. USB Token Transaction USB Transaction USB Register Summary Table 4-7. USB Register SummaryDedicated to host mode Table 4-9. 16- Interrupt Status Register Definitions USB Register DefinitionsInterrupt Status Register Table 4-8. Interrupt Status Register USB Reset Enable/Disable USBRST InterruptSleep Timer Error Condition Error Register Table 4-10. Error Interrupt Status RegisterTable 4-11. 16- Error Interrupt Status Register Definitions PID check field failed Error interrupt with two functionsData Field Received Not 8 Bits CRC16 Failure Table 4-13. Status Register Definitions Live USB Differential Receiver JSTATE SignalLive USB Single Ended Zero Signal Table 4-12. Status Register BDT PDD Reset USB Reset SignalHost Mode Enable valid for host mode only Resume Signaling Address Register Table 4-14. Address RegisterTable 4-15. 16- Address Register Definitions Frame Number Frame Number RegistersTable 4-16. Frame Number Register Table 4-17. Frame Number Register Definitions Token Register Table 4-20. Valid PID Tokens Endpoint for Token CommandTable 4-18. Token Register Table 4-19. Token Register Definitions Table 4-22. Endpoint Control Register Definitions Endpoint Control RegistersEndpoint Enable Table 4-21. Endpoint Control Registers Table 4-23. Endpoint Control Register Definitions Host Mode Operation Figure 3. Enable Host Mode and Configure a Target Device Sample Host Mode Operations Figure 4. Full-Speed Bulk Data Transfers to a Target Device Figure 4-5. Pull-up/Pull-down USB USB Pull-up/Pull-down Resistors Clock CLK USB Interface SignalsUSB Output Enable HOST Mode Enable 5 CAN Controllers Arbitration and Error Checking CANBUS BackgroundData Exchanges and Communication Table 5-1. Bit Rates for Different Cable Lengths CANBUS Speed and Length Register CAN Register SummariesRegister Summary Hex Offset Register Table 5-4. Detailed CAN Register Map Detailed CAN Register Map Hex Offset Acceptance Filter Enable Register Register Sending a Message CAN Register DefinitionsTX Message Registers Figure 5-1. TX Message Routing Table 5-7. TxMessage0Data Tx Message RegistersTable 5-5. TxMessage0ID28 Table 5-6. TxMessage0ID12 Message Data Table 5-12. TxMessage0Ctrl FlagsTable 5-13. TxMessage0 Register Definitions Message Identifier for Both Standard and Extended Messages Figure 5-2. RX Message Routing RX Message Registers Table 5-16. RxMessageID12 Rx Message RegistersTable 5-14. RxMessageID28 Table 5-15. Rx Message ID28 Register Definitions Table 5-23. Rx Message Data 23 Register Definitions Table 5-20. Rx Message DataTable 5-21. Rx Message Data 39 Register Definitions Table 5-22. Rx Message Data Table 5-29. Rx Message Msg Flags Register Definitions Table 5-26. RxMessage RTRTable 5-27. Rx Message RTR Register Definitions Table 5-28. Rx Message Msg Flags Table 5-32. Error Status Error Count and Status RegistersTable 5-30. Tx/Rx Error Count Table 5-31. Tx\Rx Error Count Register Definitions txlevel10 Table 5-34. Tx/Rx Message Level RegisterTable 5-35. Tx/Rx Message Level Register Definitions rxlevel10 Format Error Interrupt FlagsNote The reset value of this register’s bits is indeterminate CRC Error Bus Off State − int2n group error interrupts Interrupt Enable RegistersTable 5-38. Interrupt Enable Registers Table 5-39. Interrupt Enable Register Definitions Overload Condition − int3n group diagnostic interrupts CAN Operating ModeTable 5-40. Interrupt Enable Registers Table 5-41. Interrupt Enable Register Definitions Table 5-42. Bit Rate Divisor Register CAN Configuration RegistersConfiguration Bit Rate Figure 5-3. CAN Operating Mode Cfgsjw Table 5-44. Configuration RegisterTable 5-45. Configuration Register Definitions Overwrite Last Message time quanta TQ Bit Timetseg1 + tseg2 + Table 5-48. Acceptance Mask 0 Register Acceptance Filter and Acceptance Code MaskTable 5-46. Acceptance Filter Enable Register Table 5-47. Acceptance Filter Enable Register Definitions D5556 Table 5-50. Acceptance Mask Register IDTable 5-51. Acceptance Mask Register ID12 Definitions Table 5-52. Acceptance Mask Register Data Table 5-57. Acceptance Mask Register ID12 Definitions Table 5-54. Acceptance Code RegisterTable 5-55. Acceptance Code Register Definitions Table 5-56. Acceptance Mask Register ID12 Table 5-61. Arbitration Lost Capture Register Definitions CANbus AnalysisArbitration Lost Capture Register Table 5-60. Arbitration Lost Capture Register Errorcode Error Capture RegisterTable 5-62. Error Capture Register Table 5-63. Error Capture Register Definitions Stuff Bit Inserted Table 5-65. Error Capture Register DefinitionsFrame Reference Register Table 5-64. Frame Reference Register Figure 5-5. CAN Bus Interface CAN Bus InterfaceInterface Connections Figure 5-6. CAN Connector +24V Figure 5-7. Power for CAN+5CAN GNDCAN 0.01uf Figure 5-8. CAN Transceiver and Isolation Circuits