Bit Time, Tseg1 +, Tseg2 +, Time quanta TQ

The following relations exist for bit time, time quanta, time segments ½, and the data sampling point.

Figure 5-4. Bit Time, Time Quanta, and Sample Point Relationships

Bit Time

1	tseg1 + 1	tseg2 + 1

time quanta (TQ)		Sample Point

Bittime = (1+ ( tseg1 + 1) + (tseg2 + 1)) x timequanta timequanta = (bitrate +1) / fclk

e.g., for 1Mbps with fclk = 8Mhz, set bitrate = 0, tseg1 = 3 and tseg2 = 2

Observe the following conditions when setting tseg1 and tseg2:

tseg1=0 and tseg1=1 are not allowed

tseg2=0 is not allowed; tseg2=1 is only allowed in direct sampling mode.

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Lantronix DSTni-EX manual Bit Time, tseg1 +, tseg2 +, time quanta TQ, Sample Point

Contents

Section Five DSTni-EX User GuidePage Lantronix Copyright & TrademarkTechnical Support Master Distributor Warranty 1 About This User Guide Contents2 SPI Controller 3 I2C Controller 5 CAN Controllers List of Tables Table 3-17. Clock Control Register List of Figures 1 About This User Guide Conventions Intended AudienceNavigating Online Notes Notes are information requiring attention Organization Theory of Operation 2 SPI ControllerSPI Background DSTni SPI Controller Table 2-1. SPI Controller Register Summary SPI Controller Register Summary SPIDATA Register SPI Controller Register DefinitionsRESET Table 2-2. SPIDATA Register Interrupt Request Enable CTL RegisterPhase Select Wire-O Table 2-6. SPISTAT Register SPISTAT RegisterTable 2-7. SPISTAT Register Definitions Interrupt Request Table 2-10. BCNT Bit Settings SPISSEL RegisterSelectO Signal Table 2-8. SPISSEL Register DVDCNTRHI DVDCNTRLO RegisterTable 2-11. DVDCNTRLO Register Table 2-12. DVDCNTRLO Register Definitions 3 I2C Controller Features I2C Background Block DiagramFigure 3-1. DSTni I2C Controller Block Diagram Operating Modes I2C ControllerMaster Transmit Mode Code Table 3-1. Master Transmit Status CodesI2C State Microprocessor Response Table 3-2. Codes After Servicing Interrupts Master Transmit Servicing the Interrupt Table 3-3. Status Codes After Each Data Byte Transmits Transmitting Each Data ByteAll Bytes Transmit Completely Master Receive Mode Table 3-4. Master Receive Status Codes Table 3-5. Codes After Servicing Interrupt Master Receive Table 3-6. Codes After Receiving Each Data Byte Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Bus Clock Speed Bus Clock ConsiderationsClock Synchronization Bus Arbitration I2C Controller Register Summary Programmer’s ReferenceResetting the I2C Controller Table 3-7. I 2C Controller Register Summary Slave Address Register I2C Controller Register DefinitionsGeneral Call Address Enable Table 3-8. Slave Address Register Table 3-10. Data Register Data Register Table 3-12. Control Register Control RegisterTable 3-13. Control Register Definitions Extended Slave Address Table 3-14. Status Register Status Register Table 3-16. Status Codes Table 3-15. Status Register DefinitionsStatus Code Table 3-17. Clock Control Register Clock Control RegisterTable 3-18. Clock Control Register Definitions Extended Slave Address Register Software Reset RegisterTable 3-21. Software Reset Register Table 3-22. Software Reset Register Definitions 4 USB Controller USB Interrupt USB BackgroundUSB Core Serial Interface Engine Digital Phase Lock Loop Logic USB Hardware/Software InterfaceMicroprocessor Interface Buffer Descriptor Table Rx vs. Tx as a Target Device or Host Figure 4-1. Buffer Descriptor Table Addressing BDT Entries Table 4-1. USB Data DirectionTable 4-2. 16-Bit USB Address Table 4-3. 16-Bit USB Address Definitions USB Controller Determines… Table 4-4. BDT Data Used by USB Controller and MicroprocessorMicroprocessor Determines… Table 4-5. USB Buffer Descriptor Format BD Owner Table 4-6. USB Buffer Descriptor Format DefinitionsDATA0/1 Transmit or Receive USB Ownership Figure 4-2. USB Token Transaction USB Transaction Table 4-7. USB Register Summary USB Register SummaryDedicated to host mode Interrupt Status Register USB Register DefinitionsTable 4-8. Interrupt Status Register Table 4-9. 16- Interrupt Status Register Definitions Sleep Timer Enable/Disable USBRST InterruptError Condition USB Reset Table 4-10. Error Interrupt Status Register Error RegisterTable 4-11. 16- Error Interrupt Status Register Definitions Data Field Received Not 8 Bits Error interrupt with two functionsCRC16 Failure PID check field failed Live USB Single Ended Zero Signal Live USB Differential Receiver JSTATE SignalTable 4-12. Status Register Table 4-13. Status Register Definitions Host Mode Enable valid for host mode only USB Reset SignalResume Signaling BDT PDD Reset Table 4-14. Address Register Address RegisterTable 4-15. 16- Address Register Definitions Table 4-16. Frame Number Register Frame Number RegistersTable 4-17. Frame Number Register Definitions Frame Number Token Register Table 4-18. Token Register Endpoint for Token CommandTable 4-19. Token Register Definitions Table 4-20. Valid PID Tokens Endpoint Enable Endpoint Control RegistersTable 4-21. Endpoint Control Registers Table 4-22. Endpoint Control Register Definitions Table 4-23. Endpoint Control Register Definitions Host Mode Operation Figure 3. Enable Host Mode and Configure a Target Device Sample Host Mode Operations Figure 4. Full-Speed Bulk Data Transfers to a Target Device Figure 4-5. Pull-up/Pull-down USB USB Pull-up/Pull-down Resistors USB Output Enable USB Interface SignalsHOST Mode Enable Clock CLK 5 CAN Controllers CANBUS Background Arbitration and Error CheckingData Exchanges and Communication Table 5-1. Bit Rates for Different Cable Lengths CANBUS Speed and Length Register Summary CAN Register SummariesHex Offset Register Register Table 5-4. Detailed CAN Register Map Detailed CAN Register Map Hex Offset Acceptance Filter Enable Register Register TX Message Registers CAN Register DefinitionsFigure 5-1. TX Message Routing Sending a Message Table 5-5. TxMessage0ID28 Tx Message RegistersTable 5-6. TxMessage0ID12 Table 5-7. TxMessage0Data Table 5-13. TxMessage0 Register Definitions Table 5-12. TxMessage0Ctrl FlagsMessage Identifier for Both Standard and Extended Messages Message Data Figure 5-2. RX Message Routing RX Message Registers Table 5-14. RxMessageID28 Rx Message RegistersTable 5-15. Rx Message ID28 Register Definitions Table 5-16. RxMessageID12 Table 5-21. Rx Message Data 39 Register Definitions Table 5-20. Rx Message DataTable 5-22. Rx Message Data Table 5-23. Rx Message Data 23 Register Definitions Table 5-27. Rx Message RTR Register Definitions Table 5-26. RxMessage RTRTable 5-28. Rx Message Msg Flags Table 5-29. Rx Message Msg Flags Register Definitions Table 5-30. Tx/Rx Error Count Error Count and Status RegistersTable 5-31. Tx\Rx Error Count Register Definitions Table 5-32. Error Status Table 5-35. Tx/Rx Message Level Register Definitions Table 5-34. Tx/Rx Message Level Registerrxlevel10 txlevel10 Note The reset value of this register’s bits is indeterminate Interrupt FlagsCRC Error Format Error Table 5-38. Interrupt Enable Registers Interrupt Enable RegistersTable 5-39. Interrupt Enable Register Definitions Bus Off State − int2n group error interrupts Table 5-40. Interrupt Enable Registers CAN Operating ModeTable 5-41. Interrupt Enable Register Definitions Overload Condition − int3n group diagnostic interrupts Configuration Bit Rate CAN Configuration RegistersFigure 5-3. CAN Operating Mode Table 5-42. Bit Rate Divisor Register Table 5-45. Configuration Register Definitions Table 5-44. Configuration RegisterOverwrite Last Message Cfgsjw tseg1 + Bit Timetseg2 + time quanta TQ Table 5-46. Acceptance Filter Enable Register Acceptance Filter and Acceptance Code MaskTable 5-47. Acceptance Filter Enable Register Definitions Table 5-48. Acceptance Mask 0 Register Table 5-51. Acceptance Mask Register ID12 Definitions Table 5-50. Acceptance Mask Register IDTable 5-52. Acceptance Mask Register Data D5556 Table 5-55. Acceptance Code Register Definitions Table 5-54. Acceptance Code RegisterTable 5-56. Acceptance Mask Register ID12 Table 5-57. Acceptance Mask Register ID12 Definitions Arbitration Lost Capture Register CANbus AnalysisTable 5-60. Arbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register Definitions Table 5-62. Error Capture Register Error Capture RegisterTable 5-63. Error Capture Register Definitions Errorcode Frame Reference Register Table 5-65. Error Capture Register DefinitionsTable 5-64. Frame Reference Register Stuff Bit Inserted Interface Connections CAN Bus InterfaceFigure 5-6. CAN Connector Figure 5-5. CAN Bus Interface +5CAN Figure 5-7. Power for CANGNDCAN +24V 0.01uf Figure 5-8. CAN Transceiver and Isolation Circuits

Figure 5-4. Bit Time, Time Quanta, and Sample Point Relationships

Bit Time

tseg1 + 1

tseg2 + 1

time quanta (TQ)

Sample Point