Lantronix DSTni-EX manual USB Hardware/Software Interface, Microprocessor Interface

Microprocessor Interface

The USB microprocessor interface is made up of a slave interface and a master interface.

The slave interface consists of a number of USB control and configuration registers. USB internal registers can be accessed using a simple microprocessor interface.

The master interface is the integrated DMA controller that transfers packet data to and from memory. The DMA controller facilitates USB endpoint data transfer efficiently, while limiting microprocessor involvement.

Digital Phase Lock Loop Logic

The USB Digital Phase Lock Loop (DPLL) maintains a 12 MHz clock source that is locked to the USB data steam. The DPLL requires a 48 MHz clock to 4x oversample the USB data stream and detect transitions. These transitions are used to synthesize a nominally 12 MHz USB clock.

The DPLL also detects single-ended zeros, end-of-packet strobes, and NRZI decoding of the serial data stream for the Rx Logic. All DPLL outputs are synchronized to the 12 MHz clock to connect seamlessly to the USB core.

USB Hardware/Software Interface

The USB block combines hardware and software to efficiently implement USB target applications. While the USB SIE handles the low-level USB Protocol Layer, the CPU handles the higher level USB Device Framework, buffer management, and peripheral dependent functions.

The hardware/software interface of the USB provides both a slave interface and a master interface.

The slave interface consists of the Control Registers Block (CRB), which configure the USB and provide status and interrupts to the microprocessor.

The master interface is the USB integrated DMA controller, which interrogates the Buffer Descriptor Table (BDT), and transfers USB data to or from system memory. The Buffer Descriptor Table (BDT) allows the microprocessor and USB to efficiently manage multiple endpoints with very little CPU overhead.

Buffer Descriptor Table

The USB uses a Buffer Descriptor Table (BDT) in system memory to manage USB endpoint communications efficiently. The BDT resides on a 256-byte boundary in system memory and is pointed to by the BDT Page register.

Every endpoint direction requires two 4-byte Buffer Descriptor entries. Therefore, a system with 16 fully bidirectional endpoints requires 256 bytes of system memory to implement the BDT. The two Buffer Descriptor (BD) entries allow for an EVEN BD and ODD BD entry for each endpoint direction. This allows the microprocessor to process one BD while the USB processes the other BD. Double buffering BDs in this way lets the USB easily transfer data at the maximum throughput provided by USB.

32