Register | Lantronix DSTni-EX manual

0x7a

0x78

0x76

0x74 116d

0x72

0x70

0x6e

0x6c

0x6a

0x68

0x66

0x64

0x62

0x60

0x5e

0x5c

0x5a

0x58

0x56

0x54

0x52

Hex Offset

Frame Reference Register

Error Capture Register

Arbitration Lost Capture Register

///

///

Acceptance Code Register 2

///

///

Acceptance Mask Register 2

///

///

Acceptance Code Register 1

///

///

Acceptance Mask Register 1

///

///

Acceptance Code Register 0

///

///

Acceptance Mask Register 0

Register

Stuff_Ind

err_code_2

///

D55

ID12

ID28

D55

ID12

ID28

D55

ID12

ID28

D55

ID12

ID28

D55

ID12

ID28

D55

ID12

ID28

15

RX_Bit

err_code_1

///

D54

ID11

ID27

D54

ID11

ID27

D54

ID11

ID27

D54

ID11

ID27

D54

ID11

ID27

D54

ID11

ID27

14

TX_Bit

err_code_0

///

D53

ID10

ID26

D53

ID10

ID26

D53

ID10

ID26

D53

ID10

ID26

D53

ID10

ID26

D53

ID10

ID26

13

frame_ref_4

frame_ref_4

frame_ref_4

D52

ID09

ID25

D52

ID09

ID25

D52

ID09

ID25

D52

ID09

ID25

D52

ID09

ID25

D52

ID09

ID25

12

frame_ref_3

frame_ref_3

frame_ref_3

D51

ID08

ID24

D51

ID08

ID24

D51

ID08

ID24

D51

ID08

ID24

D51

ID08

ID24

D51

ID08

ID24

11

frame_ref_2

frame_ref_2

frame_ref_2

D50

ID07

ID23

D50

ID07

ID23

D50

ID07

ID23

D50

ID07

ID23

D50

ID07

ID23

D50

ID07

ID23

10

frame_ref_1

frame_ref_1

frame_ref_1

D49

ID06

ID22

D49

ID06

ID22

D49

ID06

ID22

D49

ID06

ID22

D49

ID06

ID22

D49

ID06

ID22

9

62

frame_ref_0

frame_ref_0

frame_ref_0

D48

ID05

ID21

D48

ID05

ID21

D48

ID05

ID21

D48

ID05

ID21

D48

ID05

ID21

D48

ID05

ID21

8

RX_Mode

TX_Mode

///

D63

ID04

ID20

D63

ID04

ID20

D63

ID04

ID20

D63

ID04

ID20

D63

ID04

ID20

D63

ID04

ID20

7

TX_Mode

RX_Mode

///

D62

ID03

ID19

D62

ID03

ID19

D62

ID03

ID19

D62

ID03

ID19

D62

ID03

ID19

D62

ID03

ID19

6

frame_bit_5

frame_bit_5

frame_bit_5

D61

ID02

ID18

D61

ID02

ID18

D61

ID02

ID18

D61

ID02

ID18

D61

ID02

ID18

D61

ID02

ID18

5

frame_bit_4

frame_bit_4

frame_bit_4

D60

ID01

ID17

D60

ID01

ID17

D60

ID01

ID17

D60

ID01

ID17

D60

ID01

ID17

D60

ID01

ID17

4

frame_bit_3

frame_bit_3

frame_bit_3

D59

ID00

ID16

D59

ID00

ID16

D59

ID00

ID16

D59

ID00

ID16

D59

ID00

ID16

D59

ID00

ID16

3

frame_bit_2

frame_bit_2

frame_bit_2

D58

IDE

ID15

D58

IDE

ID15

D58

IDE

ID15

D58

IDE

ID15

D58

IDE

ID15

D58

IDE

ID15

2

frame_bit_1

frame_bit_1

frame_bit_1

D57

RTR

ID14

D57

RTR

ID14

D57

RTR

ID14

D57

RTR

ID14

D57

RTR

ID14

D57

RTR

ID14

1

frame_bit_0

frame_bit_0

frame_bit_0

D56

///

ID13

D56

///

ID13

D56

///

ID13

D56

///

ID13

D56

///

ID13

D56

///

ID13

0

Image 70

Lantronix DSTni-EX manual Register

Contents

DSTni-EX User Guide Section FivePage Technical Support Copyright & TrademarkLantronix Master Distributor Warranty 2 SPI Controller Contents1 About This User Guide 3 I2C Controller List of Tables 5 CAN Controllers Table 3-17. Clock Control Register List of Figures 1 About This User Guide Navigating Online Intended AudienceConventions Notes Notes are information requiring attention Organization SPI Background 2 SPI ControllerTheory of Operation DSTni SPI Controller SPI Controller Register Summary Table 2-1. SPI Controller Register Summary RESET SPI Controller Register DefinitionsSPIDATA Register Table 2-2. SPIDATA Register Phase Select CTL RegisterInterrupt Request Enable Wire-O Table 2-7. SPISTAT Register Definitions SPISTAT RegisterTable 2-6. SPISTAT Register Interrupt Request SelectO Signal SPISSEL RegisterTable 2-10. BCNT Bit Settings Table 2-8. SPISSEL Register Table 2-11. DVDCNTRLO Register DVDCNTRLO RegisterDVDCNTRHI Table 2-12. DVDCNTRLO Register Definitions Features 3 I2C Controller I2C Background Block DiagramFigure 3-1. DSTni I2C Controller Block Diagram Operating Modes I2C ControllerMaster Transmit Mode I2C State Table 3-1. Master Transmit Status CodesCode Microprocessor Response Servicing the Interrupt Table 3-2. Codes After Servicing Interrupts Master Transmit All Bytes Transmit Completely Transmitting Each Data ByteTable 3-3. Status Codes After Each Data Byte Transmits Master Receive Mode Table 3-4. Master Receive Status Codes Table 3-5. Codes After Servicing Interrupt Master Receive Table 3-6. Codes After Receiving Each Data Byte Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Clock Synchronization Bus Clock ConsiderationsBus Clock Speed Bus Arbitration Resetting the I2C Controller Programmer’s ReferenceI2C Controller Register Summary Table 3-7. I 2C Controller Register Summary General Call Address Enable I2C Controller Register DefinitionsSlave Address Register Table 3-8. Slave Address Register Data Register Table 3-10. Data Register Table 3-13. Control Register Definitions Control RegisterTable 3-12. Control Register Extended Slave Address Status Register Table 3-14. Status Register Table 3-16. Status Codes Table 3-15. Status Register DefinitionsStatus Code Table 3-17. Clock Control Register Clock Control RegisterTable 3-18. Clock Control Register Definitions Table 3-21. Software Reset Register Software Reset RegisterExtended Slave Address Register Table 3-22. Software Reset Register Definitions 4 USB Controller USB Core USB BackgroundUSB Interrupt Serial Interface Engine Microprocessor Interface USB Hardware/Software InterfaceDigital Phase Lock Loop Logic Buffer Descriptor Table Figure 4-1. Buffer Descriptor Table Rx vs. Tx as a Target Device or Host Table 4-2. 16-Bit USB Address Table 4-1. USB Data DirectionAddressing BDT Entries Table 4-3. 16-Bit USB Address Definitions Microprocessor Determines… Table 4-4. BDT Data Used by USB Controller and MicroprocessorUSB Controller Determines… Table 4-5. USB Buffer Descriptor Format DATA0/1 Transmit or Receive Table 4-6. USB Buffer Descriptor Format DefinitionsBD Owner USB Ownership USB Transaction Figure 4-2. USB Token Transaction Table 4-7. USB Register Summary USB Register SummaryDedicated to host mode Table 4-8. Interrupt Status Register USB Register DefinitionsInterrupt Status Register Table 4-9. 16- Interrupt Status Register Definitions Error Condition Enable/Disable USBRST InterruptSleep Timer USB Reset Table 4-10. Error Interrupt Status Register Error RegisterTable 4-11. 16- Error Interrupt Status Register Definitions CRC16 Failure Error interrupt with two functionsData Field Received Not 8 Bits PID check field failed Table 4-12. Status Register Live USB Differential Receiver JSTATE SignalLive USB Single Ended Zero Signal Table 4-13. Status Register Definitions Resume Signaling USB Reset SignalHost Mode Enable valid for host mode only BDT PDD Reset Table 4-14. Address Register Address RegisterTable 4-15. 16- Address Register Definitions Table 4-17. Frame Number Register Definitions Frame Number RegistersTable 4-16. Frame Number Register Frame Number Token Register Table 4-19. Token Register Definitions Endpoint for Token CommandTable 4-18. Token Register Table 4-20. Valid PID Tokens Table 4-21. Endpoint Control Registers Endpoint Control RegistersEndpoint Enable Table 4-22. Endpoint Control Register Definitions Host Mode Operation Table 4-23. Endpoint Control Register Definitions Sample Host Mode Operations Figure 3. Enable Host Mode and Configure a Target Device Figure 4. Full-Speed Bulk Data Transfers to a Target Device USB Pull-up/Pull-down Resistors Figure 4-5. Pull-up/Pull-down USB HOST Mode Enable USB Interface SignalsUSB Output Enable Clock CLK 5 CAN Controllers CANBUS Background Arbitration and Error CheckingData Exchanges and Communication CANBUS Speed and Length Table 5-1. Bit Rates for Different Cable Lengths Hex Offset CAN Register SummariesRegister Summary Register Hex Offset Detailed CAN Register Map Table 5-4. Detailed CAN Register Map Acceptance Filter Enable Register Hex Offset Register Figure 5-1. TX Message Routing CAN Register DefinitionsTX Message Registers Sending a Message Table 5-6. TxMessage0ID12 Tx Message RegistersTable 5-5. TxMessage0ID28 Table 5-7. TxMessage0Data Message Identifier for Both Standard and Extended Messages Table 5-12. TxMessage0Ctrl FlagsTable 5-13. TxMessage0 Register Definitions Message Data RX Message Registers Figure 5-2. RX Message Routing Table 5-15. Rx Message ID28 Register Definitions Rx Message RegistersTable 5-14. RxMessageID28 Table 5-16. RxMessageID12 Table 5-22. Rx Message Data Table 5-20. Rx Message DataTable 5-21. Rx Message Data 39 Register Definitions Table 5-23. Rx Message Data 23 Register Definitions Table 5-28. Rx Message Msg Flags Table 5-26. RxMessage RTRTable 5-27. Rx Message RTR Register Definitions Table 5-29. Rx Message Msg Flags Register Definitions Table 5-31. Tx\Rx Error Count Register Definitions Error Count and Status RegistersTable 5-30. Tx/Rx Error Count Table 5-32. Error Status rxlevel10 Table 5-34. Tx/Rx Message Level RegisterTable 5-35. Tx/Rx Message Level Register Definitions txlevel10 CRC Error Interrupt FlagsNote The reset value of this register’s bits is indeterminate Format Error Table 5-39. Interrupt Enable Register Definitions Interrupt Enable RegistersTable 5-38. Interrupt Enable Registers Bus Off State − int2n group error interrupts Table 5-41. Interrupt Enable Register Definitions CAN Operating ModeTable 5-40. Interrupt Enable Registers Overload Condition − int3n group diagnostic interrupts Figure 5-3. CAN Operating Mode CAN Configuration RegistersConfiguration Bit Rate Table 5-42. Bit Rate Divisor Register Overwrite Last Message Table 5-44. Configuration RegisterTable 5-45. Configuration Register Definitions Cfgsjw tseg2 + Bit Timetseg1 + time quanta TQ Table 5-47. Acceptance Filter Enable Register Definitions Acceptance Filter and Acceptance Code MaskTable 5-46. Acceptance Filter Enable Register Table 5-48. Acceptance Mask 0 Register Table 5-52. Acceptance Mask Register Data Table 5-50. Acceptance Mask Register IDTable 5-51. Acceptance Mask Register ID12 Definitions D5556 Table 5-56. Acceptance Mask Register ID12 Table 5-54. Acceptance Code RegisterTable 5-55. Acceptance Code Register Definitions Table 5-57. Acceptance Mask Register ID12 Definitions Table 5-60. Arbitration Lost Capture Register CANbus AnalysisArbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register Definitions Table 5-63. Error Capture Register Definitions Error Capture RegisterTable 5-62. Error Capture Register Errorcode Table 5-64. Frame Reference Register Table 5-65. Error Capture Register DefinitionsFrame Reference Register Stuff Bit Inserted Figure 5-6. CAN Connector CAN Bus InterfaceInterface Connections Figure 5-5. CAN Bus Interface GNDCAN Figure 5-7. Power for CAN+5CAN +24V Figure 5-8. CAN Transceiver and Isolation Circuits 0.01uf