Manuals / Lantronix / Computer Equipment / Computer Hardware

Lantronix DSTni-EX manual 14. Status Register

Models: DSTni-EX

1 95

Download 95 pages 56.41 Kb

Page 34

Bits	Field Name	Description
2	AAK	Acknowledge
		1 = send Acknowledge (LOW level on SDA) during acknowledge clock pulse on
		the I2C bus if:
		−The entire 7-bit slave address or the first or second bytes of a 10-bit slave
		address are received.
		− The general call address is received and the GCE bit in the ADDR register is
		set to one.
		− A data byte is received in master or slave mode.
		0 in slave transmitter mode = send Not Acknowledge (HIGH level on SDA) when
		a data byte is received in master or slave mode. After this byte transmits, the I2C
		controller enters state C8h and returns to idle state. The I2C controller does not
		respond as a slave unless AAK is set.
1:0	///	Reserved

Status Register

The Status register is a Read Only register that contains a 5-bit status code in the five most- significant bits. The three least-significant bits are always zero. This register can contain any of the 31 status codes in Table 3-16. When this register contains the status code F8h:

No relevant status information is available. No interrupt is generated.

The IFLG bit in the Control register is not set.

All other status codes correspond to a defined state of the I2C controller, as described in Table 3-16.

When entering each of these states, the corresponding status code appears in this register and the IFLG bit in the Control register is set. When the IFLG bit clears, the status code returns to F8h

If an illegal condition occurs on the I2C bus, the bus enters the bus error state (status code 00h). To recover from this state, set the STP bit in the Control register and clear the IFLG bit. The I2C controller then returns to the idle state. No STOP condition transmits on the I2C bus.

Note: The STP and STA bits can be set to 1 at the same time to recover from the bus error, causing the I2C controller to send a START.

Table 3-14. Status Register

BIT	7	6		5		4		3		2		1		0
OFFSET							D006
							D006

FIELD			STATUS CODE							///		///		///
			STATUS CODE							///		///		///

RESET	0	0		0		0		0		0		0		0
RW	R	R		R		R		R		R		R		R

26

Image 34

Lantronix DSTni-EX manual 14. Status Register

Contents

DSTni-EX User Guide Section FivePage Technical Support Copyright & TrademarkLantronix Master DistributorWarranty 2 SPI Controller Contents1 About This User Guide 3 I2C ControllerList of Tables 5 CAN ControllersTable 3-17. Clock Control Register List of Figures 1 About This User Guide Navigating Online Intended AudienceConventions Notes Notes are information requiring attentionOrganization SPI Background 2 SPI ControllerTheory of Operation DSTni SPI ControllerSPI Controller Register Summary Table 2-1. SPI Controller Register SummaryRESET SPI Controller Register DefinitionsSPIDATA Register Table 2-2. SPIDATA RegisterInterrupt Request Enable CTL RegisterRESET Phase SelectTable 2-6. SPISTAT Register SPISTAT RegisterRESET Table 2-7. SPISTAT Register DefinitionsRESET SPISSEL RegisterTable 2-10. BCNT Bit Settings SelectO SignalRESET DVDCNTRLO RegisterDVDCNTRHI RESETFeatures 3 I2C ControllerFigure 3-1. DSTni I2C Controller Block Diagram Block DiagramI2C Background Theory of OperationOperating Modes I2C ControllerMaster Transmit Mode I2C State Table 3-1. Master Transmit Status CodesCode Microprocessor ResponseServicing the Interrupt Table 3-2. Codes After Servicing Interrupts Master TransmitAll Bytes Transmit Completely Transmitting Each Data ByteTable 3-3. Status Codes After Each Data Byte Transmits Master Receive ModeI 2C State Table 3-4. Master Receive Status CodesCode Microprocessor ResponseServicing the Interrupt Table 3-5. Codes After Servicing Interrupt Master ReceiveTable 3-6. Codes After Receiving Each Data Byte Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Clock Synchronization Bus Clock ConsiderationsBus Clock Speed Bus ArbitrationResetting the I2C Controller Programmer’s ReferenceI2C Controller Register Summary Table 3-7. I 2C Controller Register SummaryRESET I2C Controller Register DefinitionsSlave Address Register General Call Address EnableData Register Table 3-10. Data RegisterTable 3-13. Control Register Definitions Control RegisterTable 3-12. Control Register Extended Slave AddressStatus Register Table 3-14. Status RegisterField Name Table 3-15. Status Register DefinitionsBits DescriptionTable 3-17. Clock Control Register Clock Control RegisterTable 3-18. Clock Control Register Definitions Table 3-21. Software Reset Register Software Reset RegisterExtended Slave Address Register Table 3-22. Software Reset Register Definitions4 USB Controller FeaturesUSB Core USB BackgroundUSB Interrupt Theory of OperationMicroprocessor Interface USB Hardware/Software InterfaceDigital Phase Lock Loop Logic Buffer Descriptor TableFigure 4-1. Buffer Descriptor Table Rx vs. Tx as a Target Device or HostTable 4-2. 16-Bit USB Address Table 4-1. USB Data DirectionAddressing BDT Entries Table 4-3. 16-Bit USB Address DefinitionsMicroprocessor Determines… Table 4-4. BDT Data Used by USB Controller and MicroprocessorUSB Controller Determines… Table 4-5. USB Buffer Descriptor FormatDATA0/1 Transmit or Receive Table 4-6. USB Buffer Descriptor Format DefinitionsBD Owner USB OwnershipUSB Transaction Figure 4-2. USB Token TransactionTable 4-7. USB Register Summary USB Register SummaryDedicated to host mode Table 4-8. Interrupt Status Register USB Register DefinitionsInterrupt Status Register Table 4-9. 16- Interrupt Status Register DefinitionsError Condition Enable/Disable USBRST InterruptSleep Timer USB ResetTable 4-10. Error Interrupt Status Register Error RegisterTable 4-11. 16- Error Interrupt Status Register Definitions CRC16 Failure Error interrupt with two functionsData Field Received Not 8 Bits PID check field failedStatus Register Live USB Differential Receiver JSTATE SignalLive USB Single Ended Zero Signal Table 4-12. Status RegisterResume Signaling USB Reset SignalHost Mode Enable valid for host mode only BDT PDD ResetTable 4-14. Address Register Address RegisterTable 4-15. 16- Address Register Definitions Table 4-16. Frame Number Register Frame Number RegistersRESET Table 4-17. Frame Number Register DefinitionsToken Register Table 4-18. Token Register RESETEndpoint for Token Command Table 4-19. Token Register DefinitionsTable 4-21. Endpoint Control Registers Endpoint Control RegistersEndpoint Enable Table 4-22. Endpoint Control Register DefinitionsHost Mode Operation Table 4-23. Endpoint Control Register DefinitionsSample Host Mode Operations Figure 3. Enable Host Mode and Configure a Target DeviceFigure 4. Full-Speed Bulk Data Transfers to a Target Device USB Pull-up/Pull-down Resistors Figure 4-5. Pull-up/Pull-down USBHOST Mode Enable USB Interface SignalsUSB Output Enable Clock CLK5 CAN Controllers CANBUS Background Arbitration and Error CheckingData Exchanges and Communication Features CANBUS Speed and LengthTable 5-1. Bit Rates for Different Cable Lengths Hex Offset CAN Register SummariesRegister Summary RegisterHex Offset RegisterDetailed CAN Register Map Table 5-4. Detailed CAN Register MapAcceptance Filter Enable Register Hex OffsetRegister Figure 5-1. TX Message Routing CAN Register DefinitionsTX Message Registers Sending a MessageTable 5-6. TxMessage0ID12 Tx Message RegistersTable 5-5. TxMessage0ID28 Table 5-7. TxMessage0DataMessage Identifier for Both Standard and Extended Messages Table 5-12. TxMessage0Ctrl FlagsTable 5-13. TxMessage0 Register Definitions Message DataRX Message Registers Figure 5-2. RX Message RoutingTable 5-15. Rx Message ID28 Register Definitions Rx Message RegistersTable 5-14. RxMessageID28 Table 5-16. RxMessageID12Table 5-22. Rx Message Data Table 5-20. Rx Message DataTable 5-21. Rx Message Data 39 Register Definitions Table 5-23. Rx Message Data 23 Register DefinitionsTable 5-28. Rx Message Msg Flags Table 5-26. RxMessage RTRTable 5-27. Rx Message RTR Register Definitions Table 5-29. Rx Message Msg Flags Register DefinitionsTable 5-31. Tx\Rx Error Count Register Definitions Error Count and Status RegistersTable 5-30. Tx/Rx Error Count Table 5-32. Error StatusReserved Table 5-34. Tx/Rx Message Level RegisterTable 5-35. Tx/Rx Message Level Register Definitions rxlevel10CRC Error Interrupt FlagsNote The reset value of this register’s bits is indeterminate Format ErrorTable 5-39. Interrupt Enable Register Definitions Interrupt Enable RegistersTable 5-38. Interrupt Enable Registers Bus Off State − int2n group error interruptsTable 5-41. Interrupt Enable Register Definitions CAN Operating ModeTable 5-40. Interrupt Enable Registers Overload Condition − int3n group diagnostic interruptsFigure 5-3. CAN Operating Mode CAN Configuration RegistersConfiguration Bit Rate Table 5-42. Bit Rate Divisor RegisterOverwrite Last Message Table 5-44. Configuration RegisterTable 5-45. Configuration Register Definitions Cfgsjwtseg2 + Bit Timetseg1 + time quanta TQTable 5-47. Acceptance Filter Enable Register Definitions Acceptance Filter and Acceptance Code MaskTable 5-46. Acceptance Filter Enable Register Table 5-48. Acceptance Mask 0 RegisterTable 5-52. Acceptance Mask Register Data Table 5-50. Acceptance Mask Register IDTable 5-51. Acceptance Mask Register ID12 Definitions Message DataTable 5-56. Acceptance Mask Register ID12 Table 5-54. Acceptance Code RegisterTable 5-55. Acceptance Code Register Definitions Table 5-57. Acceptance Mask Register ID12 DefinitionsTable 5-60. Arbitration Lost Capture Register CANbus AnalysisArbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register DefinitionsTable 5-63. Error Capture Register Definitions Error Capture RegisterTable 5-62. Error Capture Register ErrorcodeFrame Reference Register Note The reset value of this register’s bits is indeterminateTable 5-65. Error Capture Register Definitions Table 5-64. Frame Reference RegisterFigure 5-6. CAN Connector CAN Bus InterfaceInterface Connections Figure 5-5. CAN Bus InterfaceGNDCAN Figure 5-7. Power for CAN+5CAN +24VFigure 5-8. CAN Transceiver and Isolation Circuits 0.01uf