Lantronix DSTni-EX 34. Tx/Rx Message Level Register, 35. Tx/Rx Message Level Register Definitions

Table 5-34. Tx/Rx Message Level Register

BIT	15	14	13	12	11	10		9	8	7	6	5	4	3	2	1	0
OFFSET									44h
FIELD							///							RL1	RL0	TL1	TL0
RESET	0	0	0	0	0	0		0	0	0	0	0	0	0	0	0	0
R/W	R/W	R/W	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

	Table 5-35. Tx/Rx Message Level Register Definitions
Bits		Field Name	Description
15:4		///	Reserved
3:1		RL[1:0]	rx_level[1:0]
			Sets the rx_msg interrupt threshold:
			0	= at least 1 message in receive FIFO
			1	= at least 2 messages in receive FIFO.
			2	= at least 3 messages in receive FIFO.
			3	= at least 4 messages in receive FIFO.
1:0		TL[1:0]	tx_level[1:0]
			Sets the tx_msg interrupt threshold:
			0	= all tx buffers are empty.
			1	= minimum 2 empty buffers.
			2	= minimum 1 empty buffer.
			3	= not applicable.

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