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Lantronix DSTni-EX Transmitting Each Data Byte, 3. Status Codes After Each Data Byte Transmits

Models: DSTni-EX

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Transmitting Each Data Byte

After each data byte transmits, the IFLG is set, and one of the three status codes in Table 3-3is in the Status register.

	Table 3-3. Status Codes After Each Data Byte Transmits

Code	I2C State		Microprocessor Response	Next I2C Action
28h	Data byte transmitted,		Write byte to DAT, clear IFLG	Transmit data byte, receive ACK
	ACK received		OR
			OR
			Set STA, clear IFLG	Transmit repeated START
			OR
			Set STP, clear IFLG	Transmit STOP
			OR
			Set STA and STP, clear IFLG	Transmit START then STOP
30h	Data byte transmitted,		Same as code 28h	Same as code 28h
	ACK not received
38h	Arbitration lost		Clear IFLG	Return to idle
			OR
			Set STA, clear IFLG	Transmit START when bus free

All Bytes Transmit Completely

When all bytes transmit completely, set the STP bit by writing a 1 to this bit in the Control register. The I2C controller:

Transmits a STOP condition Clears the STP bit Returns to the idle state

Master Receive Mode

In master receive mode, the I2C controller receives a number of bytes from a slave transmitter. After the START condition transmits:

1.The IFLG bit is set and status code 08h is in the Status register.

2.The Data register has the slave address (or the first part of a 10-bit slave address), with the least-significant bits set to 1 to signify a read.

3.The IFLG bit is 0 and prompts the transfer to continue.

4.When the 7-bit slave address (or the first part of a 10-bit address) and the read bit transmit, the IFLG bit is set again.

A number of status codes are possible in the Status register, as shown in Table 3-4.

Note: In 10-bit addressing, after the first part of a 10-bit address and the read bit successfully transmit, the status code is 40h or 48h. If a repeated START condition transmits, the status code is 10h instead of 08h.

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Lantronix DSTni-EX manual Transmitting Each Data Byte, 3. Status Codes After Each Data Byte Transmits, Master Receive Mode

Contents

DSTni-EX User Guide Section FivePage Copyright & Trademark LantronixTechnical Support Master DistributorWarranty Contents 1 About This User Guide2 SPI Controller 3 I2C ControllerList of Tables 5 CAN ControllersTable 3-17. Clock Control Register List of Figures 1 About This User Guide Intended Audience ConventionsNavigating Online Notes Notes are information requiring attentionOrganization 2 SPI Controller Theory of OperationSPI Background DSTni SPI ControllerSPI Controller Register Summary Table 2-1. SPI Controller Register SummarySPI Controller Register Definitions SPIDATA RegisterRESET Table 2-2. SPIDATA RegisterCTL Register RESETInterrupt Request Enable Phase SelectSPISTAT Register RESETTable 2-6. SPISTAT Register Table 2-7. SPISTAT Register DefinitionsSPISSEL Register Table 2-10. BCNT Bit SettingsRESET SelectO SignalDVDCNTRLO Register DVDCNTRHIRESET RESETFeatures 3 I2C ControllerBlock Diagram I2C BackgroundFigure 3-1. DSTni I2C Controller Block Diagram Theory of OperationI2C Controller Operating ModesMaster Transmit Mode Table 3-1. Master Transmit Status Codes CodeI2C State Microprocessor ResponseServicing the Interrupt Table 3-2. Codes After Servicing Interrupts Master TransmitTransmitting Each Data Byte Table 3-3. Status Codes After Each Data Byte TransmitsAll Bytes Transmit Completely Master Receive ModeTable 3-4. Master Receive Status Codes CodeI 2C State Microprocessor ResponseServicing the Interrupt Table 3-5. Codes After Servicing Interrupt Master ReceiveReceiving Each Data Byte Table 3-6. Codes After Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Bus Clock Considerations Bus Clock SpeedClock Synchronization Bus ArbitrationProgrammer’s Reference I2C Controller Register SummaryResetting the I2C Controller Table 3-7. I 2C Controller Register SummaryI2C Controller Register Definitions Slave Address RegisterRESET General Call Address EnableData Register Table 3-10. Data RegisterControl Register Table 3-12. Control RegisterTable 3-13. Control Register Definitions Extended Slave AddressStatus Register Table 3-14. Status RegisterTable 3-15. Status Register Definitions BitsField Name DescriptionClock Control Register Table 3-17. Clock Control RegisterTable 3-18. Clock Control Register Definitions Software Reset Register Extended Slave Address RegisterTable 3-21. Software Reset Register Table 3-22. Software Reset Register Definitions4 USB Controller FeaturesUSB Background USB InterruptUSB Core Theory of OperationUSB Hardware/Software Interface Digital Phase Lock Loop LogicMicroprocessor Interface Buffer Descriptor TableFigure 4-1. Buffer Descriptor Table Rx vs. Tx as a Target Device or HostTable 4-1. USB Data Direction Addressing BDT EntriesTable 4-2. 16-Bit USB Address Table 4-3. 16-Bit USB Address DefinitionsTable 4-4. BDT Data Used by USB Controller and Microprocessor USB Controller Determines…Microprocessor Determines… Table 4-5. USB Buffer Descriptor FormatTable 4-6. USB Buffer Descriptor Format Definitions BD OwnerDATA0/1 Transmit or Receive USB OwnershipUSB Transaction Figure 4-2. USB Token TransactionUSB Register Summary Table 4-7. USB Register SummaryDedicated to host mode USB Register Definitions Interrupt Status RegisterTable 4-8. Interrupt Status Register Table 4-9. 16- Interrupt Status Register DefinitionsEnable/Disable USBRST Interrupt Sleep TimerError Condition USB ResetError Register Table 4-10. Error Interrupt Status RegisterTable 4-11. 16- Error Interrupt Status Register Definitions Error interrupt with two functions Data Field Received Not 8 BitsCRC16 Failure PID check field failedLive USB Differential Receiver JSTATE Signal Live USB Single Ended Zero SignalStatus Register Table 4-12. Status RegisterUSB Reset Signal Host Mode Enable valid for host mode onlyResume Signaling BDT PDD ResetAddress Register Table 4-14. Address RegisterTable 4-15. 16- Address Register Definitions Frame Number Registers RESETTable 4-16. Frame Number Register Table 4-17. Frame Number Register DefinitionsToken Register RESET Endpoint for Token CommandTable 4-18. Token Register Table 4-19. Token Register DefinitionsEndpoint Control Registers Endpoint EnableTable 4-21. Endpoint Control Registers Table 4-22. Endpoint Control Register DefinitionsHost Mode Operation Table 4-23. Endpoint Control Register DefinitionsSample Host Mode Operations Figure 3. Enable Host Mode and Configure a Target DeviceFigure 4. Full-Speed Bulk Data Transfers to a Target Device USB Pull-up/Pull-down Resistors Figure 4-5. Pull-up/Pull-down USBUSB Interface Signals USB Output EnableHOST Mode Enable Clock CLK5 CAN Controllers Arbitration and Error Checking CANBUS BackgroundData Exchanges and Communication CANBUS Speed and Length FeaturesTable 5-1. Bit Rates for Different Cable Lengths CAN Register Summaries Register SummaryHex Offset RegisterHex Offset RegisterDetailed CAN Register Map Table 5-4. Detailed CAN Register MapAcceptance Filter Enable Register Hex OffsetRegister CAN Register Definitions TX Message RegistersFigure 5-1. TX Message Routing Sending a MessageTx Message Registers Table 5-5. TxMessage0ID28Table 5-6. TxMessage0ID12 Table 5-7. TxMessage0DataTable 5-12. TxMessage0Ctrl Flags Table 5-13. TxMessage0 Register DefinitionsMessage Identifier for Both Standard and Extended Messages Message DataRX Message Registers Figure 5-2. RX Message RoutingRx Message Registers Table 5-14. RxMessageID28Table 5-15. Rx Message ID28 Register Definitions Table 5-16. RxMessageID12Table 5-20. Rx Message Data Table 5-21. Rx Message Data 39 Register DefinitionsTable 5-22. Rx Message Data Table 5-23. Rx Message Data 23 Register DefinitionsTable 5-26. RxMessage RTR Table 5-27. Rx Message RTR Register DefinitionsTable 5-28. Rx Message Msg Flags Table 5-29. Rx Message Msg Flags Register DefinitionsError Count and Status Registers Table 5-30. Tx/Rx Error CountTable 5-31. Tx\Rx Error Count Register Definitions Table 5-32. Error StatusTable 5-34. Tx/Rx Message Level Register Table 5-35. Tx/Rx Message Level Register DefinitionsReserved rxlevel10Interrupt Flags Note The reset value of this register’s bits is indeterminateCRC Error Format ErrorInterrupt Enable Registers Table 5-38. Interrupt Enable RegistersTable 5-39. Interrupt Enable Register Definitions Bus Off State − int2n group error interruptsCAN Operating Mode Table 5-40. Interrupt Enable RegistersTable 5-41. Interrupt Enable Register Definitions Overload Condition − int3n group diagnostic interruptsCAN Configuration Registers Configuration Bit RateFigure 5-3. CAN Operating Mode Table 5-42. Bit Rate Divisor RegisterTable 5-44. Configuration Register Table 5-45. Configuration Register DefinitionsOverwrite Last Message CfgsjwBit Time tseg1 +tseg2 + time quanta TQAcceptance Filter and Acceptance Code Mask Table 5-46. Acceptance Filter Enable RegisterTable 5-47. Acceptance Filter Enable Register Definitions Table 5-48. Acceptance Mask 0 RegisterTable 5-50. Acceptance Mask Register ID Table 5-51. Acceptance Mask Register ID12 DefinitionsTable 5-52. Acceptance Mask Register Data Message DataTable 5-54. Acceptance Code Register Table 5-55. Acceptance Code Register DefinitionsTable 5-56. Acceptance Mask Register ID12 Table 5-57. Acceptance Mask Register ID12 DefinitionsCANbus Analysis Arbitration Lost Capture RegisterTable 5-60. Arbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register DefinitionsError Capture Register Table 5-62. Error Capture RegisterTable 5-63. Error Capture Register Definitions ErrorcodeNote The reset value of this register’s bits is indeterminate Table 5-65. Error Capture Register DefinitionsFrame Reference Register Table 5-64. Frame Reference RegisterCAN Bus Interface Interface ConnectionsFigure 5-6. CAN Connector Figure 5-5. CAN Bus InterfaceFigure 5-7. Power for CAN +5CANGNDCAN +24VFigure 5-8. CAN Transceiver and Isolation Circuits 0.01uf