Table 5-50. Acceptance Mask Register: ID 12
BIT | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OFFSET |
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| 54h |
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FIELD | ID12 | ID11 | ID10 | ID09 | ID08 | ID07 | ID06 | ID05 | ID04 | ID03 | ID02 | ID01 | ID00 |
| RTR |
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| IDE | /// | ||||||||||||||
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RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
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| Bits | Field Name | Description |
| 15:3 | ID[28:13] | Message Data |
| 2 | IDE | Extended Identifier Bit |
| 1 | RTR | Remote Bit |
| 0 | /// | Reserved |
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Table 5-52. Acceptance Mask Register: Data 55
BIT | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OFFSET |
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| 56h |
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FIELD | D55 | D54 | D53 | D52 | D51 | D50 | D49 | D48 | D63 | D62 | D61 | D60 | D59 | D58 | D57 | D56 |
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RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
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| Table | |
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| Bits | Field Name | Description |
| 15:0 | D[55:56] | Message Data |
79