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Lantronix DSTni-EX 38. Interrupt Enable Registers, 39. Interrupt Enable Register Definitions

Models: DSTni-EX

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Interrupt Enable Registers

Interrupt Enable Registers

All interrupt sources are grouped into three groups (traffic, error and diagnostics interrupts). To enable a particular interrupt, set its enable flag to ‘ 1’ .

Table 5-38. Interrupt Enable Registers

BIT	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OFFSET								48h
FIELD			_XMIT2TX	_XMIT1TX	_XMIT0TX		_CRCERR	FORMERR	_ACKERR	STUFERR			OVRLOAD	ARBLOSS
	_MSGRX	_MSGTX	_XMIT2TX	_XMIT1TX	_XMIT0TX	_BUSOFF	_CRCERR	FORMERR	_ACKERR	STUFERR	_ERRBIT	_OVRRX	OVRLOAD	ARBLOSS	///	_ENBINT
															///

RESET	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

		Table 5-39. Interrupt Enable Register Definitions

	Bits	Field Name	Description
	15	RX_MSG	Rx Message − int1_n group (traffic interrupts)
			1	= enable flag set.
			0	= enable flag not set.
	14	TX_MSG	Tx Message − int1_n group (traffic interrupts)
			1	= enable flag set.
			0	= enable flag not set.
	13	TX_XMIT2	Tx Xmit 2 − int1_n group (traffic interrupts)
			1	= enable flag set.
			0	= enable flag not set.
	12	TX_XMIT1	Tx Xmit 1 − int1_n group (traffic interrupts)
			1	= enable flag set.
			0	= enable flag not set.
	11	TX_XMIT0	Tx Xmit 0 − int1_n group (traffic interrupts)
			1	= enable flag set.
			0	= enable flag not set.
	10	BUS_OFF	Bus Off State − int2_n group (error interrupts)
			1	= enable flag set.
			0	= enable flag not set.
	9	CRC_ERR	CRC Error − int2_n group (error interrupts)
			1	= enable flag set.
			0	= enable flag not set.
	8	FORM_ERR	Format Error − int2_n group (error interrupts)
			1	= enable flag set.
			0	= enable flag not set.
	7	ACK_ERR	Acknowledgement Error − int2_n group (error interrupts)
			1	= enable flag set.
			0	= enable flag not set.
	6	STUF_ERR	Stuffing Error − int2_n group (error interrupts)
			1	= enable flag set.
			0	= enable flag not set.
	5	BIT_ERR	Bit Error − int2_n group (error interrupts)
			1	= enable flag set.
			0	= enable flag not set.
	4	RX_OVR	Receiver Overrun − int1_n group (traffic interrupts)
			1	= enable flag set.
			0	= enable flag not set.

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Image 81

Lantronix DSTni-EX manual 38. Interrupt Enable Registers, 39. Interrupt Enable Register Definitions

Contents

Section Five DSTni-EX User GuidePage Lantronix Copyright & TrademarkTechnical Support Master DistributorWarranty 1 About This User Guide Contents2 SPI Controller 3 I2C Controller5 CAN Controllers List of TablesTable 3-17. Clock Control Register List of Figures 1 About This User Guide Conventions Intended AudienceNavigating Online Notes Notes are information requiring attentionOrganization Theory of Operation 2 SPI ControllerSPI Background DSTni SPI ControllerTable 2-1. SPI Controller Register Summary SPI Controller Register SummarySPIDATA Register SPI Controller Register DefinitionsRESET Table 2-2. SPIDATA RegisterRESET CTL RegisterInterrupt Request Enable Phase SelectRESET SPISTAT RegisterTable 2-6. SPISTAT Register Table 2-7. SPISTAT Register DefinitionsTable 2-10. BCNT Bit Settings SPISSEL RegisterRESET SelectO SignalDVDCNTRHI DVDCNTRLO RegisterRESET RESET3 I2C Controller FeaturesI2C Background Block DiagramFigure 3-1. DSTni I2C Controller Block Diagram Theory of OperationI2C Controller Operating ModesMaster Transmit Mode Code Table 3-1. Master Transmit Status CodesI2C State Microprocessor ResponseTable 3-2. Codes After Servicing Interrupts Master Transmit Servicing the InterruptTable 3-3. Status Codes After Each Data Byte Transmits Transmitting Each Data ByteAll Bytes Transmit Completely Master Receive ModeCode Table 3-4. Master Receive Status CodesI 2C State Microprocessor ResponseTable 3-5. Codes After Servicing Interrupt Master Receive Servicing the InterruptReceiving Each Data Byte Table 3-6. Codes After Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Bus Clock Speed Bus Clock ConsiderationsClock Synchronization Bus ArbitrationI2C Controller Register Summary Programmer’s ReferenceResetting the I2C Controller Table 3-7. I 2C Controller Register SummarySlave Address Register I2C Controller Register DefinitionsRESET General Call Address EnableTable 3-10. Data Register Data RegisterTable 3-12. Control Register Control RegisterTable 3-13. Control Register Definitions Extended Slave AddressTable 3-14. Status Register Status RegisterBits Table 3-15. Status Register DefinitionsField Name DescriptionClock Control Register Table 3-17. Clock Control RegisterTable 3-18. Clock Control Register Definitions Extended Slave Address Register Software Reset RegisterTable 3-21. Software Reset Register Table 3-22. Software Reset Register DefinitionsFeatures 4 USB ControllerUSB Interrupt USB BackgroundUSB Core Theory of OperationDigital Phase Lock Loop Logic USB Hardware/Software InterfaceMicroprocessor Interface Buffer Descriptor TableRx vs. Tx as a Target Device or Host Figure 4-1. Buffer Descriptor TableAddressing BDT Entries Table 4-1. USB Data DirectionTable 4-2. 16-Bit USB Address Table 4-3. 16-Bit USB Address DefinitionsUSB Controller Determines… Table 4-4. BDT Data Used by USB Controller and MicroprocessorMicroprocessor Determines… Table 4-5. USB Buffer Descriptor FormatBD Owner Table 4-6. USB Buffer Descriptor Format DefinitionsDATA0/1 Transmit or Receive USB OwnershipFigure 4-2. USB Token Transaction USB TransactionUSB Register Summary Table 4-7. USB Register SummaryDedicated to host mode Interrupt Status Register USB Register DefinitionsTable 4-8. Interrupt Status Register Table 4-9. 16- Interrupt Status Register DefinitionsSleep Timer Enable/Disable USBRST InterruptError Condition USB ResetError Register Table 4-10. Error Interrupt Status RegisterTable 4-11. 16- Error Interrupt Status Register Definitions Data Field Received Not 8 Bits Error interrupt with two functionsCRC16 Failure PID check field failedLive USB Single Ended Zero Signal Live USB Differential Receiver JSTATE SignalStatus Register Table 4-12. Status RegisterHost Mode Enable valid for host mode only USB Reset SignalResume Signaling BDT PDD ResetAddress Register Table 4-14. Address RegisterTable 4-15. 16- Address Register Definitions RESET Frame Number RegistersTable 4-16. Frame Number Register Table 4-17. Frame Number Register DefinitionsToken Register Endpoint for Token Command RESETTable 4-18. Token Register Table 4-19. Token Register DefinitionsEndpoint Enable Endpoint Control RegistersTable 4-21. Endpoint Control Registers Table 4-22. Endpoint Control Register DefinitionsTable 4-23. Endpoint Control Register Definitions Host Mode OperationFigure 3. Enable Host Mode and Configure a Target Device Sample Host Mode OperationsFigure 4. Full-Speed Bulk Data Transfers to a Target Device Figure 4-5. Pull-up/Pull-down USB USB Pull-up/Pull-down ResistorsUSB Output Enable USB Interface SignalsHOST Mode Enable Clock CLK5 CAN Controllers Arbitration and Error Checking CANBUS BackgroundData Exchanges and Communication CANBUS Speed and Length FeaturesTable 5-1. Bit Rates for Different Cable Lengths Register Summary CAN Register SummariesHex Offset RegisterRegister Hex OffsetTable 5-4. Detailed CAN Register Map Detailed CAN Register MapHex Offset Acceptance Filter Enable RegisterRegister TX Message Registers CAN Register DefinitionsFigure 5-1. TX Message Routing Sending a MessageTable 5-5. TxMessage0ID28 Tx Message RegistersTable 5-6. TxMessage0ID12 Table 5-7. TxMessage0DataTable 5-13. TxMessage0 Register Definitions Table 5-12. TxMessage0Ctrl FlagsMessage Identifier for Both Standard and Extended Messages Message DataFigure 5-2. RX Message Routing RX Message RegistersTable 5-14. RxMessageID28 Rx Message RegistersTable 5-15. Rx Message ID28 Register Definitions Table 5-16. RxMessageID12Table 5-21. Rx Message Data 39 Register Definitions Table 5-20. Rx Message DataTable 5-22. Rx Message Data Table 5-23. Rx Message Data 23 Register DefinitionsTable 5-27. Rx Message RTR Register Definitions Table 5-26. RxMessage RTRTable 5-28. Rx Message Msg Flags Table 5-29. Rx Message Msg Flags Register DefinitionsTable 5-30. Tx/Rx Error Count Error Count and Status RegistersTable 5-31. Tx\Rx Error Count Register Definitions Table 5-32. Error StatusTable 5-35. Tx/Rx Message Level Register Definitions Table 5-34. Tx/Rx Message Level RegisterReserved rxlevel10Note The reset value of this register’s bits is indeterminate Interrupt FlagsCRC Error Format ErrorTable 5-38. Interrupt Enable Registers Interrupt Enable RegistersTable 5-39. Interrupt Enable Register Definitions Bus Off State − int2n group error interruptsTable 5-40. Interrupt Enable Registers CAN Operating ModeTable 5-41. Interrupt Enable Register Definitions Overload Condition − int3n group diagnostic interruptsConfiguration Bit Rate CAN Configuration RegistersFigure 5-3. CAN Operating Mode Table 5-42. Bit Rate Divisor RegisterTable 5-45. Configuration Register Definitions Table 5-44. Configuration RegisterOverwrite Last Message Cfgsjwtseg1 + Bit Timetseg2 + time quanta TQTable 5-46. Acceptance Filter Enable Register Acceptance Filter and Acceptance Code MaskTable 5-47. Acceptance Filter Enable Register Definitions Table 5-48. Acceptance Mask 0 RegisterTable 5-51. Acceptance Mask Register ID12 Definitions Table 5-50. Acceptance Mask Register IDTable 5-52. Acceptance Mask Register Data Message DataTable 5-55. Acceptance Code Register Definitions Table 5-54. Acceptance Code RegisterTable 5-56. Acceptance Mask Register ID12 Table 5-57. Acceptance Mask Register ID12 DefinitionsArbitration Lost Capture Register CANbus AnalysisTable 5-60. Arbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register DefinitionsTable 5-62. Error Capture Register Error Capture RegisterTable 5-63. Error Capture Register Definitions ErrorcodeTable 5-65. Error Capture Register Definitions Note The reset value of this register’s bits is indeterminateFrame Reference Register Table 5-64. Frame Reference RegisterInterface Connections CAN Bus InterfaceFigure 5-6. CAN Connector Figure 5-5. CAN Bus Interface+5CAN Figure 5-7. Power for CANGNDCAN +24V0.01uf Figure 5-8. CAN Transceiver and Isolation Circuits