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Lantronix DSTni-EX manual Acceptance Filter Enable Register, Hex Offset

Models: DSTni-EX

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61

0x50

0x4e

0x4c

0x4a

0x48

0x46

0x44

0x42

0x40

0x3e

0x3c

0x3a

0x38

0x36

0x34

0x32

0x30

Hex Offset

Acceptance Filter Enable Register

CAN tsegs

CAN Bit Rate Divisor

CAN Mode

IRQ Enb. Reg.

IRQ flags

TX/ RX Msglevel

Error Status

TX & RX Error Cnt

RX Msg Flags

///

///

///

///

///

///

RX Msg

Register

///

ovr_wrt_msg

///

///

rx_msg

rx_msg

///

///

rx_er_cnt_7

///

///

D07

D23

D39

D55

ID12

ID28

15

///

cfg_tseg2_2

///

///

tx_msg

tx_msg

///

///

rx_er_cnt_6

///

///

D06

D22

D38

D54

ID11

ID27

14

///

cfg_tseg2_1

///

///

tx_xmit2

tx_xmit2

///

///

rx_er_cnt_5

///

///

D05

D21

D37

D53

ID10

ID26

13

///

cfg_tseg2_0

///

///

tx_xmit1

tx_xmit1

///

///

rx_er_cnt_4

///

///

D04

D20

D36

D52

ID09

ID25

12

///

cfg_tseg1_3

///

///

tx_xmit0

tx_xmit0

///

///

rx_er_cnt_3

///

///

D03

D19

D35

D51

ID08

ID24

11

///

cfg_tseg1_2

cfg_bitrate_10

///

bus_off

bus_off

///

///

rx_er_cnt_2

///

AFI_2

D02

D18

D34

D50

ID07

ID23

10

///

cfg_tseg1_1

cfg_bitrate_9

///

crc_error

crc_error

///

///

rx_er_cnt_1

///

AFI_1

D01

D17

D33

D49

ID06

ID22

9

///

cfg_tseg1_0

cfg_bitrate_8

///

form_error

form_error

///

///

rx_er_cnt_0

///

AFI_0

D00

D16

D32

D48

ID05

ID21

8

///

///

cfg_bitrate_7

///

ack_error

ack_error

///

///

tx_er_cnt_7

Fifo_Lvl_2

///

D15

D31

D47

D63

ID04

ID20

7

///

///

cfg_bitrate_6

///

stuff_error

stuff_error

///

///

tx_er_cnt_6

Fifo_Lvl_1

///

D14

D30

D46

D62

ID03

ID19

6

///

///

cfg_bitrate_5

///

bit_error

bit_error

///

///

tx_er_cnt_5

Fifo_Lvl_0

RTR

D13

D29

D45

D61

ID02

ID18

5

///

auto-restart

cfg_bitrate_4

///

rx_ovr

rx_ovr

///

///

tx_er_cnt_4

///

IDE

D12

D28

D44

D60

ID01

ID17

4

///

cfg_sjw_1

cfg_bitrate_3

///

ovr_load

ovr_load

rx_level_1

Rxgte96

tx_er_cnt_3

///

DLC_3

D11

D27

D43

D59

ID00

ID16

3

AFE_2

cfg_sjw_1

cfg_bitrate_2

Loop_Back

arb_loss

arb_loss

rx_level_0

Txgte96

tx_er_cnt_2

///

DLC_2

D10

D26

D42

D58

///

ID15

2

AFE_1

sample_mode

cfg_bitrate_1

Passive

///

///

tx_level_1

error_stat_1

tx_er_cnt_1

///

DLC_1

D09

D25

D41

D57

///

ID14

1

AFE_0

edge_mode

cfg_bitrate_0

Run

int_enable

///

tx_level_0

error_stat_0

tx_er_cnt_0

MsgAval

DLC_0

D08

D24

D40

D56

///

ID13

0

Image 69

Lantronix DSTni-EX manual Acceptance Filter Enable Register, Hex Offset

Contents

Section Five DSTni-EX User GuidePage Lantronix Copyright & TrademarkTechnical Support Master DistributorWarranty 1 About This User Guide Contents2 SPI Controller 3 I2C Controller5 CAN Controllers List of TablesTable 3-17. Clock Control Register List of Figures 1 About This User Guide Conventions Intended AudienceNavigating Online Notes Notes are information requiring attentionOrganization Theory of Operation 2 SPI ControllerSPI Background DSTni SPI ControllerTable 2-1. SPI Controller Register Summary SPI Controller Register SummarySPIDATA Register SPI Controller Register DefinitionsRESET Table 2-2. SPIDATA RegisterRESET CTL RegisterInterrupt Request Enable Phase SelectRESET SPISTAT RegisterTable 2-6. SPISTAT Register Table 2-7. SPISTAT Register DefinitionsTable 2-10. BCNT Bit Settings SPISSEL RegisterRESET SelectO SignalDVDCNTRHI DVDCNTRLO RegisterRESET RESET3 I2C Controller FeaturesI2C Background Block DiagramFigure 3-1. DSTni I2C Controller Block Diagram Theory of OperationI2C Controller Operating ModesMaster Transmit Mode Code Table 3-1. Master Transmit Status CodesI2C State Microprocessor ResponseTable 3-2. Codes After Servicing Interrupts Master Transmit Servicing the InterruptTable 3-3. Status Codes After Each Data Byte Transmits Transmitting Each Data ByteAll Bytes Transmit Completely Master Receive ModeCode Table 3-4. Master Receive Status CodesI 2C State Microprocessor ResponseTable 3-5. Codes After Servicing Interrupt Master Receive Servicing the InterruptReceiving Each Data Byte Table 3-6. Codes After Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Bus Clock Speed Bus Clock ConsiderationsClock Synchronization Bus ArbitrationI2C Controller Register Summary Programmer’s ReferenceResetting the I2C Controller Table 3-7. I 2C Controller Register SummarySlave Address Register I2C Controller Register DefinitionsRESET General Call Address EnableTable 3-10. Data Register Data RegisterTable 3-12. Control Register Control RegisterTable 3-13. Control Register Definitions Extended Slave AddressTable 3-14. Status Register Status RegisterBits Table 3-15. Status Register DefinitionsField Name DescriptionClock Control Register Table 3-17. Clock Control RegisterTable 3-18. Clock Control Register Definitions Extended Slave Address Register Software Reset RegisterTable 3-21. Software Reset Register Table 3-22. Software Reset Register DefinitionsFeatures 4 USB ControllerUSB Interrupt USB BackgroundUSB Core Theory of OperationDigital Phase Lock Loop Logic USB Hardware/Software InterfaceMicroprocessor Interface Buffer Descriptor TableRx vs. Tx as a Target Device or Host Figure 4-1. Buffer Descriptor TableAddressing BDT Entries Table 4-1. USB Data DirectionTable 4-2. 16-Bit USB Address Table 4-3. 16-Bit USB Address DefinitionsUSB Controller Determines… Table 4-4. BDT Data Used by USB Controller and MicroprocessorMicroprocessor Determines… Table 4-5. USB Buffer Descriptor FormatBD Owner Table 4-6. USB Buffer Descriptor Format DefinitionsDATA0/1 Transmit or Receive USB OwnershipFigure 4-2. USB Token Transaction USB TransactionUSB Register Summary Table 4-7. USB Register SummaryDedicated to host mode Interrupt Status Register USB Register DefinitionsTable 4-8. Interrupt Status Register Table 4-9. 16- Interrupt Status Register DefinitionsSleep Timer Enable/Disable USBRST InterruptError Condition USB ResetError Register Table 4-10. Error Interrupt Status RegisterTable 4-11. 16- Error Interrupt Status Register Definitions Data Field Received Not 8 Bits Error interrupt with two functionsCRC16 Failure PID check field failedLive USB Single Ended Zero Signal Live USB Differential Receiver JSTATE SignalStatus Register Table 4-12. Status RegisterHost Mode Enable valid for host mode only USB Reset SignalResume Signaling BDT PDD ResetAddress Register Table 4-14. Address RegisterTable 4-15. 16- Address Register Definitions RESET Frame Number RegistersTable 4-16. Frame Number Register Table 4-17. Frame Number Register DefinitionsToken Register Endpoint for Token Command RESETTable 4-18. Token Register Table 4-19. Token Register DefinitionsEndpoint Enable Endpoint Control RegistersTable 4-21. Endpoint Control Registers Table 4-22. Endpoint Control Register DefinitionsTable 4-23. Endpoint Control Register Definitions Host Mode OperationFigure 3. Enable Host Mode and Configure a Target Device Sample Host Mode OperationsFigure 4. Full-Speed Bulk Data Transfers to a Target Device Figure 4-5. Pull-up/Pull-down USB USB Pull-up/Pull-down ResistorsUSB Output Enable USB Interface SignalsHOST Mode Enable Clock CLK5 CAN Controllers Arbitration and Error Checking CANBUS BackgroundData Exchanges and Communication CANBUS Speed and Length FeaturesTable 5-1. Bit Rates for Different Cable Lengths Register Summary CAN Register SummariesHex Offset RegisterRegister Hex OffsetTable 5-4. Detailed CAN Register Map Detailed CAN Register MapHex Offset Acceptance Filter Enable RegisterRegister TX Message Registers CAN Register DefinitionsFigure 5-1. TX Message Routing Sending a MessageTable 5-5. TxMessage0ID28 Tx Message RegistersTable 5-6. TxMessage0ID12 Table 5-7. TxMessage0DataTable 5-13. TxMessage0 Register Definitions Table 5-12. TxMessage0Ctrl FlagsMessage Identifier for Both Standard and Extended Messages Message DataFigure 5-2. RX Message Routing RX Message RegistersTable 5-14. RxMessageID28 Rx Message RegistersTable 5-15. Rx Message ID28 Register Definitions Table 5-16. RxMessageID12Table 5-21. Rx Message Data 39 Register Definitions Table 5-20. Rx Message DataTable 5-22. Rx Message Data Table 5-23. Rx Message Data 23 Register DefinitionsTable 5-27. Rx Message RTR Register Definitions Table 5-26. RxMessage RTRTable 5-28. Rx Message Msg Flags Table 5-29. Rx Message Msg Flags Register DefinitionsTable 5-30. Tx/Rx Error Count Error Count and Status RegistersTable 5-31. Tx\Rx Error Count Register Definitions Table 5-32. Error StatusTable 5-35. Tx/Rx Message Level Register Definitions Table 5-34. Tx/Rx Message Level RegisterReserved rxlevel10Note The reset value of this register’s bits is indeterminate Interrupt FlagsCRC Error Format ErrorTable 5-38. Interrupt Enable Registers Interrupt Enable RegistersTable 5-39. Interrupt Enable Register Definitions Bus Off State − int2n group error interruptsTable 5-40. Interrupt Enable Registers CAN Operating ModeTable 5-41. Interrupt Enable Register Definitions Overload Condition − int3n group diagnostic interruptsConfiguration Bit Rate CAN Configuration RegistersFigure 5-3. CAN Operating Mode Table 5-42. Bit Rate Divisor RegisterTable 5-45. Configuration Register Definitions Table 5-44. Configuration RegisterOverwrite Last Message Cfgsjwtseg1 + Bit Timetseg2 + time quanta TQTable 5-46. Acceptance Filter Enable Register Acceptance Filter and Acceptance Code MaskTable 5-47. Acceptance Filter Enable Register Definitions Table 5-48. Acceptance Mask 0 RegisterTable 5-51. Acceptance Mask Register ID12 Definitions Table 5-50. Acceptance Mask Register IDTable 5-52. Acceptance Mask Register Data Message DataTable 5-55. Acceptance Code Register Definitions Table 5-54. Acceptance Code RegisterTable 5-56. Acceptance Mask Register ID12 Table 5-57. Acceptance Mask Register ID12 DefinitionsArbitration Lost Capture Register CANbus AnalysisTable 5-60. Arbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register DefinitionsTable 5-62. Error Capture Register Error Capture RegisterTable 5-63. Error Capture Register Definitions ErrorcodeTable 5-65. Error Capture Register Definitions Note The reset value of this register’s bits is indeterminateFrame Reference Register Table 5-64. Frame Reference RegisterInterface Connections CAN Bus InterfaceFigure 5-6. CAN Connector Figure 5-5. CAN Bus Interface+5CAN Figure 5-7. Power for CANGNDCAN +24V0.01uf Figure 5-8. CAN Transceiver and Isolation Circuits