Table 4-23. Endpoint Control Register Definitions
EP_CTL_DIS | EP_RX_EN | EP_TX_EN | Endpoint Enable / Direction Control |
/// | 0 | 0 | Disable endpoint. |
/// | 0 | 1 | Enable endpoint for TX transfer only. |
/// | 1 | 0 | Enable endpoint for RX transfer only. |
1 | 1 | 1 | Enable endpoint for RX and TX transfers. |
0 | 1 | 1 | Enable endpoint for RX and TX and control (SETUP) |
|
|
| transfers. |
Host Mode Operation
A unique feature of the USB core is its host mode logic. This logic lets devices such as digital cameras and palmtop computers work as a USB host controller. Host mode lets a peripheral such as a digital camera connect directly to a
Host mode is designed for
Host mode allows bulk, isochronous, interrupt and control transfers. Bulk data transfers are performed at nearly the full USB bus bandwidth. Support is provided for ISO transfers; however, the number of ISO streams that can be practically supported depends on the interrupt latency of the microprocessor servicing the
The USB core can operate as either a target device or in host mode. It cannot operate in both modes simultaneously.
To enable host mode, set the HOST_MODE_EN bit in the Status register (see Status Register on page 43). Host mode also uses the following registers:
Token Register on page 47
SOF Threshold register on page 47
During host mode, only endpoint zero is used. Software must disable all other endpoints.
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