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Lantronix DSTni-EX I2C Controller Register Definitions, Slave Address Register, Offset, Extended

Models: DSTni-EX

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I2C Controller Register Definitions

Slave Address Register

Table 3-8. Slave Address Register

BIT

7

6

5

4

3

2

1

0

OFFSET

D000

EXTENDED

Enable

ADDRESS

1

1

1

1

0

SLAX9

SLAX8

AddressCallGeneral

FIELD

SLA6

SLA5

SLA4

SLA3

SLA2

SLA1

SLA0

GCE

RESET

0

0

0

0

0

0

0

0

RW

RW

RW

RW

RW

RW

RW

RW

RW

Table 3-9. Address Register Definitions

Bits

Field Name

Description

7:1

SLA6 – SLA0

Slave Address

For 7-bit addressing, these bits are the 7-bit address of the I2C controller in slave

mode. When the I2C controller receives this address after a START condition, it

generates an interrupt and enters slave mode. (SLA6 corresponds to the first bit

received from the I2C bus.)

For 10-bit addressing, when the address received starts with F0h-F7h, the I2C

controller recognizes the correspondence to SLAX9 and SLAX8 of an extended

address, and sends an ACK. (The device does not generate an interrupt at this

point.) After receiving the next address byte, the I2C controller generates an

interrupt and enters slave mode.

0

GCE

General Call Address Enable

1 = I2C controller recognizes the general-call address at 00h (7-bit addressing).

0 = I2C controller does not recognize the general-call address at 00h (7-bit

addressing).

23

Image 31

Lantronix DSTni-EX I2C Controller Register Definitions, 8. Slave Address Register, 9. Address Register Definitions

Contents

Section Five DSTni-EX User GuidePage Master Distributor Copyright & TrademarkLantronix Technical SupportWarranty 3 I2C Controller Contents1 About This User Guide 2 SPI Controller5 CAN Controllers List of TablesTable 3-17. Clock Control Register List of Figures 1 About This User Guide Notes Notes are information requiring attention Intended AudienceConventions Navigating OnlineOrganization DSTni SPI Controller 2 SPI ControllerTheory of Operation SPI BackgroundTable 2-1. SPI Controller Register Summary SPI Controller Register SummaryTable 2-2. SPIDATA Register SPI Controller Register DefinitionsSPIDATA Register RESETPhase Select CTL RegisterRESET Interrupt Request EnableTable 2-7. SPISTAT Register Definitions SPISTAT RegisterRESET Table 2-6. SPISTAT RegisterSelectO Signal SPISSEL RegisterTable 2-10. BCNT Bit Settings RESETRESET DVDCNTRLO RegisterDVDCNTRHI RESET3 I2C Controller FeaturesTheory of Operation Block DiagramI2C Background Figure 3-1. DSTni I2C Controller Block DiagramOperating Modes I2C ControllerMaster Transmit Mode Microprocessor Response Table 3-1. Master Transmit Status CodesCode I2C StateTable 3-2. Codes After Servicing Interrupts Master Transmit Servicing the InterruptMaster Receive Mode Transmitting Each Data ByteTable 3-3. Status Codes After Each Data Byte Transmits All Bytes Transmit CompletelyMicroprocessor Response Table 3-4. Master Receive Status CodesCode I 2C StateTable 3-5. Codes After Servicing Interrupt Master Receive Servicing the InterruptTable 3-6. Codes After Receiving Each Data Byte Receiving Each Data ByteSlave Transmit Mode Slave Receive Mode Bus Arbitration Bus Clock ConsiderationsBus Clock Speed Clock SynchronizationTable 3-7. I 2C Controller Register Summary Programmer’s ReferenceI2C Controller Register Summary Resetting the I2C ControllerGeneral Call Address Enable I2C Controller Register DefinitionsSlave Address Register RESETTable 3-10. Data Register Data RegisterExtended Slave Address Control RegisterTable 3-12. Control Register Table 3-13. Control Register DefinitionsTable 3-14. Status Register Status RegisterDescription Table 3-15. Status Register DefinitionsBits Field NameTable 3-17. Clock Control Register Clock Control RegisterTable 3-18. Clock Control Register Definitions Table 3-22. Software Reset Register Definitions Software Reset RegisterExtended Slave Address Register Table 3-21. Software Reset RegisterFeatures 4 USB ControllerTheory of Operation USB BackgroundUSB Interrupt USB CoreBuffer Descriptor Table USB Hardware/Software InterfaceDigital Phase Lock Loop Logic Microprocessor InterfaceRx vs. Tx as a Target Device or Host Figure 4-1. Buffer Descriptor TableTable 4-3. 16-Bit USB Address Definitions Table 4-1. USB Data DirectionAddressing BDT Entries Table 4-2. 16-Bit USB AddressTable 4-5. USB Buffer Descriptor Format Table 4-4. BDT Data Used by USB Controller and MicroprocessorUSB Controller Determines… Microprocessor Determines…USB Ownership Table 4-6. USB Buffer Descriptor Format DefinitionsBD Owner DATA0/1 Transmit or ReceiveFigure 4-2. USB Token Transaction USB TransactionTable 4-7. USB Register Summary USB Register SummaryDedicated to host mode Table 4-9. 16- Interrupt Status Register Definitions USB Register DefinitionsInterrupt Status Register Table 4-8. Interrupt Status RegisterUSB Reset Enable/Disable USBRST InterruptSleep Timer Error ConditionTable 4-10. Error Interrupt Status Register Error RegisterTable 4-11. 16- Error Interrupt Status Register Definitions PID check field failed Error interrupt with two functionsData Field Received Not 8 Bits CRC16 FailureTable 4-12. Status Register Live USB Differential Receiver JSTATE SignalLive USB Single Ended Zero Signal Status RegisterBDT PDD Reset USB Reset SignalHost Mode Enable valid for host mode only Resume SignalingTable 4-14. Address Register Address RegisterTable 4-15. 16- Address Register Definitions Table 4-17. Frame Number Register Definitions Frame Number RegistersRESET Table 4-16. Frame Number RegisterToken Register Table 4-19. Token Register Definitions RESETEndpoint for Token Command Table 4-18. Token RegisterTable 4-22. Endpoint Control Register Definitions Endpoint Control RegistersEndpoint Enable Table 4-21. Endpoint Control RegistersTable 4-23. Endpoint Control Register Definitions Host Mode OperationFigure 3. Enable Host Mode and Configure a Target Device Sample Host Mode OperationsFigure 4. Full-Speed Bulk Data Transfers to a Target Device Figure 4-5. Pull-up/Pull-down USB USB Pull-up/Pull-down ResistorsClock CLK USB Interface SignalsUSB Output Enable HOST Mode Enable5 CAN Controllers CANBUS Background Arbitration and Error CheckingData Exchanges and Communication Features CANBUS Speed and LengthTable 5-1. Bit Rates for Different Cable Lengths Register CAN Register SummariesRegister Summary Hex OffsetRegister Hex OffsetTable 5-4. Detailed CAN Register Map Detailed CAN Register MapHex Offset Acceptance Filter Enable RegisterRegister Sending a Message CAN Register DefinitionsTX Message Registers Figure 5-1. TX Message RoutingTable 5-7. TxMessage0Data Tx Message RegistersTable 5-5. TxMessage0ID28 Table 5-6. TxMessage0ID12Message Data Table 5-12. TxMessage0Ctrl FlagsTable 5-13. TxMessage0 Register Definitions Message Identifier for Both Standard and Extended MessagesFigure 5-2. RX Message Routing RX Message RegistersTable 5-16. RxMessageID12 Rx Message RegistersTable 5-14. RxMessageID28 Table 5-15. Rx Message ID28 Register DefinitionsTable 5-23. Rx Message Data 23 Register Definitions Table 5-20. Rx Message DataTable 5-21. Rx Message Data 39 Register Definitions Table 5-22. Rx Message DataTable 5-29. Rx Message Msg Flags Register Definitions Table 5-26. RxMessage RTRTable 5-27. Rx Message RTR Register Definitions Table 5-28. Rx Message Msg FlagsTable 5-32. Error Status Error Count and Status RegistersTable 5-30. Tx/Rx Error Count Table 5-31. Tx\Rx Error Count Register Definitionsrxlevel10 Table 5-34. Tx/Rx Message Level RegisterTable 5-35. Tx/Rx Message Level Register Definitions ReservedFormat Error Interrupt FlagsNote The reset value of this register’s bits is indeterminate CRC ErrorBus Off State − int2n group error interrupts Interrupt Enable RegistersTable 5-38. Interrupt Enable Registers Table 5-39. Interrupt Enable Register DefinitionsOverload Condition − int3n group diagnostic interrupts CAN Operating ModeTable 5-40. Interrupt Enable Registers Table 5-41. Interrupt Enable Register DefinitionsTable 5-42. Bit Rate Divisor Register CAN Configuration RegistersConfiguration Bit Rate Figure 5-3. CAN Operating ModeCfgsjw Table 5-44. Configuration RegisterTable 5-45. Configuration Register Definitions Overwrite Last Messagetime quanta TQ Bit Timetseg1 + tseg2 +Table 5-48. Acceptance Mask 0 Register Acceptance Filter and Acceptance Code MaskTable 5-46. Acceptance Filter Enable Register Table 5-47. Acceptance Filter Enable Register DefinitionsMessage Data Table 5-50. Acceptance Mask Register IDTable 5-51. Acceptance Mask Register ID12 Definitions Table 5-52. Acceptance Mask Register DataTable 5-57. Acceptance Mask Register ID12 Definitions Table 5-54. Acceptance Code RegisterTable 5-55. Acceptance Code Register Definitions Table 5-56. Acceptance Mask Register ID12Table 5-61. Arbitration Lost Capture Register Definitions CANbus AnalysisArbitration Lost Capture Register Table 5-60. Arbitration Lost Capture RegisterErrorcode Error Capture RegisterTable 5-62. Error Capture Register Table 5-63. Error Capture Register DefinitionsTable 5-64. Frame Reference Register Note The reset value of this register’s bits is indeterminateTable 5-65. Error Capture Register Definitions Frame Reference RegisterFigure 5-5. CAN Bus Interface CAN Bus InterfaceInterface Connections Figure 5-6. CAN Connector+24V Figure 5-7. Power for CAN+5CAN GNDCAN0.01uf Figure 5-8. CAN Transceiver and Isolation Circuits