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DSTni-EX Sample Host Mode Operations, Enable Host Mode and Configure a Target Device
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DSTni-EX
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Block Diagram
Warranty
Enable Host Mode and Configure a Target Device
Wire-O
Reset
Overload Condition − int3n group diagnostic interrupts
Endpoint for Token Command
Error Condition
SelectO Signal
Digital Phase Lock Loop Logic
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Image 59
Sample Host Mode Operations
Figure 3. Enable Host Mode and Configure a Target Device
51
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Contents
Section Five
DSTni-EX User Guide
Page
Master Distributor
Copyright & Trademark
Lantronix
Technical Support
Warranty
3 I2C Controller
Contents
1 About This User Guide
2 SPI Controller
5 CAN Controllers
List of Tables
Table 3-17. Clock Control Register
List of Figures
1 About This User Guide
Notes Notes are information requiring attention
Intended Audience
Conventions
Navigating Online
Organization
DSTni SPI Controller
2 SPI Controller
Theory of Operation
SPI Background
Table 2-1. SPI Controller Register Summary
SPI Controller Register Summary
Table 2-2. SPIDATA Register
SPI Controller Register Definitions
SPIDATA Register
RESET
Phase Select
CTL Register
RESET
Interrupt Request Enable
Table 2-7. SPISTAT Register Definitions
SPISTAT Register
RESET
Table 2-6. SPISTAT Register
SelectO Signal
SPISSEL Register
Table 2-10. BCNT Bit Settings
RESET
RESET
DVDCNTRLO Register
DVDCNTRHI
RESET
3 I2C Controller
Features
Theory of Operation
Block Diagram
I2C Background
Figure 3-1. DSTni I2C Controller Block Diagram
Master Transmit Mode
I2C Controller
Operating Modes
Microprocessor Response
Table 3-1. Master Transmit Status Codes
Code
I2C State
Table 3-2. Codes After Servicing Interrupts Master Transmit
Servicing the Interrupt
Master Receive Mode
Transmitting Each Data Byte
Table 3-3. Status Codes After Each Data Byte Transmits
All Bytes Transmit Completely
Microprocessor Response
Table 3-4. Master Receive Status Codes
Code
I 2C State
Table 3-5. Codes After Servicing Interrupt Master Receive
Servicing the Interrupt
Slave Transmit Mode
Receiving Each Data Byte
Table 3-6. Codes After Receiving Each Data Byte
Slave Receive Mode
Bus Arbitration
Bus Clock Considerations
Bus Clock Speed
Clock Synchronization
Table 3-7. I 2C Controller Register Summary
Programmer’s Reference
I2C Controller Register Summary
Resetting the I2C Controller
General Call Address Enable
I2C Controller Register Definitions
Slave Address Register
RESET
Table 3-10. Data Register
Data Register
Extended Slave Address
Control Register
Table 3-12. Control Register
Table 3-13. Control Register Definitions
Table 3-14. Status Register
Status Register
Description
Table 3-15. Status Register Definitions
Bits
Field Name
Table 3-18. Clock Control Register Definitions
Clock Control Register
Table 3-17. Clock Control Register
Table 3-22. Software Reset Register Definitions
Software Reset Register
Extended Slave Address Register
Table 3-21. Software Reset Register
Features
4 USB Controller
Theory of Operation
USB Background
USB Interrupt
USB Core
Buffer Descriptor Table
USB Hardware/Software Interface
Digital Phase Lock Loop Logic
Microprocessor Interface
Rx vs. Tx as a Target Device or Host
Figure 4-1. Buffer Descriptor Table
Table 4-3. 16-Bit USB Address Definitions
Table 4-1. USB Data Direction
Addressing BDT Entries
Table 4-2. 16-Bit USB Address
Table 4-5. USB Buffer Descriptor Format
Table 4-4. BDT Data Used by USB Controller and Microprocessor
USB Controller Determines…
Microprocessor Determines…
USB Ownership
Table 4-6. USB Buffer Descriptor Format Definitions
BD Owner
DATA0/1 Transmit or Receive
Figure 4-2. USB Token Transaction
USB Transaction
Dedicated to host mode
USB Register Summary
Table 4-7. USB Register Summary
Table 4-9. 16- Interrupt Status Register Definitions
USB Register Definitions
Interrupt Status Register
Table 4-8. Interrupt Status Register
USB Reset
Enable/Disable USBRST Interrupt
Sleep Timer
Error Condition
Table 4-11. 16- Error Interrupt Status Register Definitions
Error Register
Table 4-10. Error Interrupt Status Register
PID check field failed
Error interrupt with two functions
Data Field Received Not 8 Bits
CRC16 Failure
Table 4-12. Status Register
Live USB Differential Receiver JSTATE Signal
Live USB Single Ended Zero Signal
Status Register
BDT PDD Reset
USB Reset Signal
Host Mode Enable valid for host mode only
Resume Signaling
Table 4-15. 16- Address Register Definitions
Address Register
Table 4-14. Address Register
Table 4-17. Frame Number Register Definitions
Frame Number Registers
RESET
Table 4-16. Frame Number Register
Token Register
Table 4-19. Token Register Definitions
RESET
Endpoint for Token Command
Table 4-18. Token Register
Table 4-22. Endpoint Control Register Definitions
Endpoint Control Registers
Endpoint Enable
Table 4-21. Endpoint Control Registers
Table 4-23. Endpoint Control Register Definitions
Host Mode Operation
Figure 3. Enable Host Mode and Configure a Target Device
Sample Host Mode Operations
Figure 4. Full-Speed Bulk Data Transfers to a Target Device
Figure 4-5. Pull-up/Pull-down USB
USB Pull-up/Pull-down Resistors
Clock CLK
USB Interface Signals
USB Output Enable
HOST Mode Enable
5 CAN Controllers
Data Exchanges and Communication
Arbitration and Error Checking
CANBUS Background
Table 5-1. Bit Rates for Different Cable Lengths
CANBUS Speed and Length
Features
Register
CAN Register Summaries
Register Summary
Hex Offset
Register
Hex Offset
Table 5-4. Detailed CAN Register Map
Detailed CAN Register Map
Hex Offset
Acceptance Filter Enable Register
Register
Sending a Message
CAN Register Definitions
TX Message Registers
Figure 5-1. TX Message Routing
Table 5-7. TxMessage0Data
Tx Message Registers
Table 5-5. TxMessage0ID28
Table 5-6. TxMessage0ID12
Message Data
Table 5-12. TxMessage0Ctrl Flags
Table 5-13. TxMessage0 Register Definitions
Message Identifier for Both Standard and Extended Messages
Figure 5-2. RX Message Routing
RX Message Registers
Table 5-16. RxMessageID12
Rx Message Registers
Table 5-14. RxMessageID28
Table 5-15. Rx Message ID28 Register Definitions
Table 5-23. Rx Message Data 23 Register Definitions
Table 5-20. Rx Message Data
Table 5-21. Rx Message Data 39 Register Definitions
Table 5-22. Rx Message Data
Table 5-29. Rx Message Msg Flags Register Definitions
Table 5-26. RxMessage RTR
Table 5-27. Rx Message RTR Register Definitions
Table 5-28. Rx Message Msg Flags
Table 5-32. Error Status
Error Count and Status Registers
Table 5-30. Tx/Rx Error Count
Table 5-31. Tx\Rx Error Count Register Definitions
rxlevel10
Table 5-34. Tx/Rx Message Level Register
Table 5-35. Tx/Rx Message Level Register Definitions
Reserved
Format Error
Interrupt Flags
Note The reset value of this register’s bits is indeterminate
CRC Error
Bus Off State − int2n group error interrupts
Interrupt Enable Registers
Table 5-38. Interrupt Enable Registers
Table 5-39. Interrupt Enable Register Definitions
Overload Condition − int3n group diagnostic interrupts
CAN Operating Mode
Table 5-40. Interrupt Enable Registers
Table 5-41. Interrupt Enable Register Definitions
Table 5-42. Bit Rate Divisor Register
CAN Configuration Registers
Configuration Bit Rate
Figure 5-3. CAN Operating Mode
Cfgsjw
Table 5-44. Configuration Register
Table 5-45. Configuration Register Definitions
Overwrite Last Message
time quanta TQ
Bit Time
tseg1 +
tseg2 +
Table 5-48. Acceptance Mask 0 Register
Acceptance Filter and Acceptance Code Mask
Table 5-46. Acceptance Filter Enable Register
Table 5-47. Acceptance Filter Enable Register Definitions
Message Data
Table 5-50. Acceptance Mask Register ID
Table 5-51. Acceptance Mask Register ID12 Definitions
Table 5-52. Acceptance Mask Register Data
Table 5-57. Acceptance Mask Register ID12 Definitions
Table 5-54. Acceptance Code Register
Table 5-55. Acceptance Code Register Definitions
Table 5-56. Acceptance Mask Register ID12
Table 5-61. Arbitration Lost Capture Register Definitions
CANbus Analysis
Arbitration Lost Capture Register
Table 5-60. Arbitration Lost Capture Register
Errorcode
Error Capture Register
Table 5-62. Error Capture Register
Table 5-63. Error Capture Register Definitions
Table 5-64. Frame Reference Register
Note The reset value of this register’s bits is indeterminate
Table 5-65. Error Capture Register Definitions
Frame Reference Register
Figure 5-5. CAN Bus Interface
CAN Bus Interface
Interface Connections
Figure 5-6. CAN Connector
+24V
Figure 5-7. Power for CAN
+5CAN
GNDCAN
0.01uf
Figure 5-8. CAN Transceiver and Isolation Circuits