Servicing the Interrupt | Lantronix DSTni-EX instruction

Servicing the Interrupt

After servicing this interrupt and transmitting the second part of the address, the Status register contains one of the codes in Table 3-5.

	Table 3-5. Codes After Servicing Interrupt (Master Receive)

Code	I2C State		Microprocessor Response	Next I2C Action
38h	Arbitration lost		Clear IFLG	Return to idle
			OR
			Set STA, clear IFLG	Transmit START when bus free
68h	Arbitration lost,		Clear IFLG, AAK=0	Receive data byte, transmit not ACK
	SLA + W received,
	ACK transmitted		OR
			Clear IFLG, AAK=1	Receive data byte, transmit ACK
78h	Arbitration lost,		Write byte to DATA, Clear IFLG,	Transmit data byte, receive ACK
	SLA + R received,		AAK=0
	ACK transmitted		OR
			OR
			Write byte to DATA, Clear IFLG,	Transmit data byte, receive ACK
			AAK=1
B0h	Arbitration lost		Clear IFLG	Return to idle
			OR
			Set STA, clear IFLG	Transmit START when bus free
E0h	Second Address byte +		Clear IFLG, AAK=0	Receive data byte, transmit not ACK
	R transmitted, ACK
	received		OR
			Clear IFLG, AAK=1	Receive data byte, transmit ACK
E8h	Second Address byte +		Clear IFLG, AAK=0	Receive data byte, transmit not ACK
	R transmitted, ACK not
	received		OR
			Clear IFLG, AAK=1	Receive data byte, transmit ACK

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Lantronix DSTni-EX manual Servicing the Interrupt, 5. Codes After Servicing Interrupt Master Receive

Contents

DSTni-EX User Guide Section FivePage Technical Support Copyright & TrademarkLantronix Master Distributor Warranty 2 SPI Controller Contents1 About This User Guide 3 I2C Controller List of Tables 5 CAN Controllers Table 3-17. Clock Control Register List of Figures 1 About This User Guide Navigating Online Intended AudienceConventions Notes Notes are information requiring attention Organization SPI Background 2 SPI ControllerTheory of Operation DSTni SPI Controller SPI Controller Register Summary Table 2-1. SPI Controller Register Summary RESET SPI Controller Register DefinitionsSPIDATA Register Table 2-2. SPIDATA Register Phase Select CTL RegisterInterrupt Request Enable Wire-O Table 2-7. SPISTAT Register Definitions SPISTAT RegisterTable 2-6. SPISTAT Register Interrupt Request SelectO Signal SPISSEL RegisterTable 2-10. BCNT Bit Settings Table 2-8. SPISSEL Register Table 2-11. DVDCNTRLO Register DVDCNTRLO RegisterDVDCNTRHI Table 2-12. DVDCNTRLO Register Definitions Features 3 I2C Controller Figure 3-1. DSTni I2C Controller Block Diagram Block DiagramI2C Background Master Transmit Mode I2C ControllerOperating Modes I2C State Table 3-1. Master Transmit Status CodesCode Microprocessor Response Servicing the Interrupt Table 3-2. Codes After Servicing Interrupts Master Transmit All Bytes Transmit Completely Transmitting Each Data ByteTable 3-3. Status Codes After Each Data Byte Transmits Master Receive Mode Table 3-4. Master Receive Status Codes Table 3-5. Codes After Servicing Interrupt Master Receive Slave Transmit Mode Receiving Each Data ByteTable 3-6. Codes After Receiving Each Data Byte Slave Receive Mode Clock Synchronization Bus Clock ConsiderationsBus Clock Speed Bus Arbitration Resetting the I2C Controller Programmer’s ReferenceI2C Controller Register Summary Table 3-7. I 2C Controller Register Summary General Call Address Enable I2C Controller Register DefinitionsSlave Address Register Table 3-8. Slave Address Register Data Register Table 3-10. Data Register Table 3-13. Control Register Definitions Control RegisterTable 3-12. Control Register Extended Slave Address Status Register Table 3-14. Status Register Status Code Table 3-15. Status Register DefinitionsTable 3-16. Status Codes Table 3-18. Clock Control Register Definitions Clock Control RegisterTable 3-17. Clock Control Register Table 3-21. Software Reset Register Software Reset RegisterExtended Slave Address Register Table 3-22. Software Reset Register Definitions 4 USB Controller USB Core USB BackgroundUSB Interrupt Serial Interface Engine Microprocessor Interface USB Hardware/Software InterfaceDigital Phase Lock Loop Logic Buffer Descriptor Table Figure 4-1. Buffer Descriptor Table Rx vs. Tx as a Target Device or Host Table 4-2. 16-Bit USB Address Table 4-1. USB Data DirectionAddressing BDT Entries Table 4-3. 16-Bit USB Address Definitions Microprocessor Determines… Table 4-4. BDT Data Used by USB Controller and MicroprocessorUSB Controller Determines… Table 4-5. USB Buffer Descriptor Format DATA0/1 Transmit or Receive Table 4-6. USB Buffer Descriptor Format DefinitionsBD Owner USB Ownership USB Transaction Figure 4-2. USB Token Transaction Dedicated to host mode USB Register SummaryTable 4-7. USB Register Summary Table 4-8. Interrupt Status Register USB Register DefinitionsInterrupt Status Register Table 4-9. 16- Interrupt Status Register Definitions Error Condition Enable/Disable USBRST InterruptSleep Timer USB Reset Table 4-11. 16- Error Interrupt Status Register Definitions Error RegisterTable 4-10. Error Interrupt Status Register CRC16 Failure Error interrupt with two functionsData Field Received Not 8 Bits PID check field failed Table 4-12. Status Register Live USB Differential Receiver JSTATE SignalLive USB Single Ended Zero Signal Table 4-13. Status Register Definitions Resume Signaling USB Reset SignalHost Mode Enable valid for host mode only BDT PDD Reset Table 4-15. 16- Address Register Definitions Address RegisterTable 4-14. Address Register Table 4-17. Frame Number Register Definitions Frame Number RegistersTable 4-16. Frame Number Register Frame Number Token Register Table 4-19. Token Register Definitions Endpoint for Token CommandTable 4-18. Token Register Table 4-20. Valid PID Tokens Table 4-21. Endpoint Control Registers Endpoint Control RegistersEndpoint Enable Table 4-22. Endpoint Control Register Definitions Host Mode Operation Table 4-23. Endpoint Control Register Definitions Sample Host Mode Operations Figure 3. Enable Host Mode and Configure a Target Device Figure 4. Full-Speed Bulk Data Transfers to a Target Device USB Pull-up/Pull-down Resistors Figure 4-5. Pull-up/Pull-down USB HOST Mode Enable USB Interface SignalsUSB Output Enable Clock CLK 5 CAN Controllers Data Exchanges and Communication Arbitration and Error CheckingCANBUS Background CANBUS Speed and Length Table 5-1. Bit Rates for Different Cable Lengths Hex Offset CAN Register SummariesRegister Summary Register Hex Offset Detailed CAN Register Map Table 5-4. Detailed CAN Register Map Acceptance Filter Enable Register Hex Offset Register Figure 5-1. TX Message Routing CAN Register DefinitionsTX Message Registers Sending a Message Table 5-6. TxMessage0ID12 Tx Message RegistersTable 5-5. TxMessage0ID28 Table 5-7. TxMessage0Data Message Identifier for Both Standard and Extended Messages Table 5-12. TxMessage0Ctrl FlagsTable 5-13. TxMessage0 Register Definitions Message Data RX Message Registers Figure 5-2. RX Message Routing Table 5-15. Rx Message ID28 Register Definitions Rx Message RegistersTable 5-14. RxMessageID28 Table 5-16. RxMessageID12 Table 5-22. Rx Message Data Table 5-20. Rx Message DataTable 5-21. Rx Message Data 39 Register Definitions Table 5-23. Rx Message Data 23 Register Definitions Table 5-28. Rx Message Msg Flags Table 5-26. RxMessage RTRTable 5-27. Rx Message RTR Register Definitions Table 5-29. Rx Message Msg Flags Register Definitions Table 5-31. Tx\Rx Error Count Register Definitions Error Count and Status RegistersTable 5-30. Tx/Rx Error Count Table 5-32. Error Status rxlevel10 Table 5-34. Tx/Rx Message Level RegisterTable 5-35. Tx/Rx Message Level Register Definitions txlevel10 CRC Error Interrupt FlagsNote The reset value of this register’s bits is indeterminate Format Error Table 5-39. Interrupt Enable Register Definitions Interrupt Enable RegistersTable 5-38. Interrupt Enable Registers Bus Off State − int2n group error interrupts Table 5-41. Interrupt Enable Register Definitions CAN Operating ModeTable 5-40. Interrupt Enable Registers Overload Condition − int3n group diagnostic interrupts Figure 5-3. CAN Operating Mode CAN Configuration RegistersConfiguration Bit Rate Table 5-42. Bit Rate Divisor Register Overwrite Last Message Table 5-44. Configuration RegisterTable 5-45. Configuration Register Definitions Cfgsjw tseg2 + Bit Timetseg1 + time quanta TQ Table 5-47. Acceptance Filter Enable Register Definitions Acceptance Filter and Acceptance Code MaskTable 5-46. Acceptance Filter Enable Register Table 5-48. Acceptance Mask 0 Register Table 5-52. Acceptance Mask Register Data Table 5-50. Acceptance Mask Register IDTable 5-51. Acceptance Mask Register ID12 Definitions D5556 Table 5-56. Acceptance Mask Register ID12 Table 5-54. Acceptance Code RegisterTable 5-55. Acceptance Code Register Definitions Table 5-57. Acceptance Mask Register ID12 Definitions Table 5-60. Arbitration Lost Capture Register CANbus AnalysisArbitration Lost Capture Register Table 5-61. Arbitration Lost Capture Register Definitions Table 5-63. Error Capture Register Definitions Error Capture RegisterTable 5-62. Error Capture Register Errorcode Table 5-64. Frame Reference Register Table 5-65. Error Capture Register DefinitionsFrame Reference Register Stuff Bit Inserted Figure 5-6. CAN Connector CAN Bus InterfaceInterface Connections Figure 5-5. CAN Bus Interface GNDCAN Figure 5-7. Power for CAN+5CAN +24V Figure 5-8. CAN Transceiver and Isolation Circuits 0.01uf