
7521Plus / N N/B MAINTENANCE
5.Pin Descriptions Of Major Components
5.1Pentium III/Celeron FC-PGA2 CPU
Alphabetical Signal Reference
Signal Name | I/O | Signal Description |
A[35:3]# | I/O | The A[35:3]# (Address) signals define a 2 36 |
| GTL+ | address space. When ADS# is active, these signals transmit the |
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| address of a transaction; when ADS# is inactive, these signals |
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| transmit transaction information. These signals must be connected to |
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| the appropriate pins/balls of both agents on the system bus. The |
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| A[35:24]# signals are protected with the AP1# parity signal, |
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| and the A[23:3]# signals are protected with the AP0# parity signal. |
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| On the |
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| agent samples A[35:3]# signals to determine its |
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| configuration. See Section 4 of this document and the PentiumII |
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| Processor Developer’s Manual for details. |
A20M# | I | If the A20M# |
| 1.5V | processor masks physical address bit 20 (A20#) before looking up a |
| Tolerant | line in any internal cache and before driving a read/write transaction |
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| on the bus. Asserting A20M# emulates the 8086 processor's address |
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| |
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| supported in Real mode. |
ADS# | I/O | The ADS# (Address Strobe) signal is asserted to indicate the validity |
| GTL+ | of a transaction address on the A[35:3]# signals. Both bus agents |
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| observe the ADS# activation to begin parity checking, protocol |
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| checking, address decode, internal snoop or deferred reply ID match |
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| operations associated with the new transaction. This signal must be |
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| connected to the appropriate pins/balls on both agents on the system |
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| bus. |
AERR# | I/O | The AERR# (Address Parity Error) signal is observed and driven by |
| GTL+ | both system bus agents, and if used, must be connected to the |
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| appropriate pins/balls of both agents on the system bus. AERR# |
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| observation is optionally enabled during |
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| enabled, a valid assertion of AERR# aborts the current transaction. |
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| If AERR# observation is disabled during |
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| central agent may handle an assertion of AERR# as appropriate to the |
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| error handling architecture of the system. |
AP[1:0]# | I/O | The AP[1:0]# (Address Parity) signals are driven by the request |
| GTL+ | initiator along with ADS#, A[35:3]#, REQ[4:0]# and RP#. AP1# |
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| covers A[35:24]#. AP0# covers A[23:3]#. A correct parity signal is |
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| high if an even number of covered signals are low and low if an odd |
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| number of covered signals are low. This allows parity to be high when |
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| all the covered signals are high. AP[1:0]# should be connected to the |
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| appropriate pins/balls on both agents on the system bus. |
BCLK | I | The BCLK (Bus Clock) signal determines the system bus frequency. |
| 2.5V | Both system bus agents must receive this signal to drive their outputs |
| Tolerant | and latch their inputs on the BCLK rising edge. All external timing |
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| parameters are specified with respect to the BCLK signal. |
Signal Name | I/O | Signal Description |
BERR# | I/O | The BERR# (Bus Error) signal is asserted to indicate an |
| GTL+ | unrecoverable error without a bus protocol violation. It may be driven |
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| by either system bus agent and must be connected to the appropriate |
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| pins/balls of both agents, if used. However, the mobile Pentium III |
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| processors do not observe assertions of the BERR# signal. |
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| BERR# assertion conditions are defined by the system configuration. |
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| Configuration options enable the BERR# driver as follows: |
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| • Enabled or disabled |
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| • Asserted optionally for internal errors along with IERR# |
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| • Asserted optionally by the request initiator of a bus transaction after |
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| it observes an error |
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| • Asserted by any bus agent when it observes an error in a bus |
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| transaction |
BINIT# | I/O- | The BINIT# (Bus Initialization) signal may be observed and driven |
| GTL+ | by both system bus agents and must be connected to the appropriate |
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| pins/balls of both agents, if used. If the BINIT# driver is enabled |
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| during the |
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| bus condition that prevents reliable future information. |
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| If BINIT# is enabled during |
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| sampled asserted, all bus state machines are reset and any data which |
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| was in transit is lost. All agents reset their rotating ID for bus |
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| arbitration to the state after reset, and internal count information is |
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| lost. The L1 and L2 caches are not affected. |
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| If BINIT# is disabled during |
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| may handle an assertion of BINIT# as appropriate to the Machine |
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| Check Architecture (MCA) of the system. |
BNR# | I/O- | The BNR# (Block Next Request) signal is used to assert a bus stall by |
| GTL+ | any bus agent that is unable to accept new bus transactions. During a |
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| bus stall, the current bus owner cannot issue any new transactions. |
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| Since multiple agents may need to request a bus stall simultaneously, |
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| BNR# is a |
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| pins/balls of both agents on the system bus. In order to avoid |
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| glitches associated with simultaneous edge transitions driven by |
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| multiple drivers, BNR# is activated on specific clock edges and |
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| sampled on specific clock edges. |
BP[3:2]# | I/O | The BP[3:2]# (Breakpoint) signals are the System Support group |
| GTL+ | Breakpoint signals. They are outputs from the processor that indicate |
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| the status of breakpoints. |
BPM[1:0]# | I/O | The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and |
| GTL+ | performance monitor signals. They are outputs from the processor |
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| that indicate the status of breakpoints and programmable counters |
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| used for monitoring processor performance. |
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