MiTAC 7521 PLUS/N Bpri#, BREQ0#, Clkref, Cmosref, Dbsy#, Defer#, Drdy#, Edgctrlp, Ferr#, Flush#

7521Plus / N N/B MAINTENANCE

5. Pin Descriptions Of Major Components

5.1 Pentium III/Celeron FC-PGA2 CPU

Alphabetical Signal Reference

Signal Name	I/O		Signal Description
BPRI#	I	The BPRI# (Bus Priority Request) signal is used to arbitrate for
	GTL+	ownership of the system bus. It must be connected to the appropriate
		pins/balls on both agents on the system bus. Observing BPRI# active
		(as asserted by the priority agent) causes the processor to stop issuing
		new requests, unless such requests are part of an ongoing locked
		operation. The priority agent keeps BPRI# asserted until all of its
		requests are completed and then releases the bus by deasserting
		BPRI#.
BREQ0#	I/O	The BREQ0# (Bus Request) signal is a processor Arbitration Bus
	GTL+	signal. The processor indicates that it wants ownership of the system
		bus by asserting the BREQ0# signal.
		During power-up configuration, the central agent must assert the
		BREQ0# bus signal. The processor samples BREQ0# on the active-
		to-inactive transition of RESET#.
BSEL[1:0]	I	The BSEL[1:0] (Select Processor System Bus Speed) signal is used to
	1.5V	configure the processor for the system bus frequency. Table 38 shows
	Tolerant	the encoding scheme for BSEL[1:0]. The only supported system bus
		frequency for the mobile Pentium III processor is 100 MHz. If
		another frequency is used or if the BSEL[1:0] signals are not driven
		with "1" then the processor is not guaranteed to function properly.
		BSEL[1:0] Encoding
		BSEL[1:0]	System Bus Frequency
		00	66 MHz
		01	100 MHz
		10	Reserved
		11	133 MHz
CLKREF	Analog	The CLKREF (System Bus Clock Reference) signal provides a
		reference voltage to define the trip point for the BCLK signal. This
		signal should be connected to a resistor divider to generate 1.25V
		from the 2.5-V supply.
CMOSREF	Analog	The CMOSREF (CMOS Reference Voltage) signal provides a DC
		level reference voltage for the CMOS input buffers. A voltage divider
		should be used to divide a stable voltage plane (e.g., 2.5V or 3.3V).
		This signal must be provided with a DC voltage that meets the
		VCMOSREF specification from Table 13.
D[63:0]#	I/O	The D[63:0]# (Data) signals are the data signals. These signals
	GTL+	provide a 64-bit data path between both system bus agents, and must
		be connected to the appropriate pins/balls on both agents. The data
		driver asserts DRDY# to indicate a valid data transfer.

Signal Name	I/O	Signal Description
DBSY#	I/O-	The DBSY# (Data Bus Busy) signal is asserted by the agent
	GTL+	responsible for driving data on the system bus to indicate that the data
		bus is in use. The data bus is released after DBSY# is deasserted. This
		signal must be connected to the appropriate pins/balls on both agents
		on the system bus.
DEFER#	I	The DEFER# (Defer) signal is asserted by an agent to indicate that
	GTL+	the transaction cannot be guaranteed in-order completion. Assertion
		of DEFER# is normally the responsibility of the addressed memory
		agent or I/O agent. This signal must be connected to the appropriate
		pins/balls on both agents on the system bus.
DEP[7:0]#	I/O	The DEP[7:0]# (Data Bus ECC Protection) signals provide optional
	GTL+	ECC protection for the data bus. They are driven by the agent
		responsible for driving D[63:0]#, and must be connected to the
		appropriate pins/balls on both agents on the system bus if they are
		used. During power-on configuration, DEP[7:0]# signals can be
		enabled for ECC checking or disabled for no checking.
DRDY#	I/O	The DRDY# (Data Ready) signal is asserted by the data driver on
	GTL+	each data transfer, indicating valid data on the data bus. In a multi-
		cycle data transfer, DRDY# can be deasserted to insert idle clocks.
		This signal must be connected to the appropriate pins/balls on both
		agents on the system bus.
EDGCTRLP	Analog	The EDGCTRLP (Edge Rate Control) signal is used to configure the
		edge rate of the GTL+ output buffers. Connect the signal to VSS with
		a 110-Ω, 1% resistor.
FERR#	O	The FERR# (Floating-point Error) signal is asserted when the
	1.5V	processor detects an unmasked floating-point error. FERR# is similar
	Tolerant	to the ERROR# signal on the Intel 387 coprocessor, and it is included
	Open-	for compatibility with systems using DOS-type floating-point error
	drain)	reporting.
FLUSH#	I	When the FLUSH# (Flush) input signal is asserted, the processor
	1.5V	writes back all internal cache lines in the Modified state and
	Tolerant	invalidates all internal cache lines. At the completion of a flush
		operation, the processor issues a Flush Acknowledge transaction. The
		processor stops caching any new data while the FLUSH# signal
		remains asserted.
		On the active-to-inactive transition of RESET#, each processor bus
		agent samples FLUSH# to determine its power-on configuration.

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