Sun Microsystems CP3220 manual Networking and I/O, NVidia MCP55

5.4Networking and I/O

Networking and I/O are provided by the following chips and interconnects:

■nVidia MCP55 (southbridge)

■PCI Express Bus

■Dual BIOS

■Trusted Platform Module

■Broadcom 5715C Gbit Ethernet chip

■Sun Sun 10 GbE Multithreaded Networking ASIC Dual 10-Gbit + Dual 1-Gbit Ethernet chip

5.4.1nVidia MCP55

The nVidia MCP55 media and communication processors (MCP) are based on a high-performance, scalable architecture with a low power design and low footprint optimized for power-constrained rack and blade servers. nVidia’s HyperTransport design integrated tightly with the AMD Opteron Direct Connect architecture to deliver 32-bit and 64-bit performance.

The Sun Netra CP3220 blade server uses one nVidia MCP55 for:

■8 lanes of PCIe to the Zone 3 Connectors

■8 lanes of PCIe to Sun 10 GbE Multithreaded Networking ASIC

■4 lanes of PCIe to the base fabric

■4 lanes of PCIe to each AMC slot

■ATA controller to the compact flash slot

■2 USB ports

■Low Pin Count (LPC) bus to the BIOS chips, H8 and TPM

■2 RGMII ports to the front panel and RTM for serial management

Chapter 5 Hardware Architecture 5-5