SUPER MICRO Computer 6014P-82 Adjacent Cache Line Prefetch, Device Configuration, KBC Clock input

Models: 6014P-8R 6014P-82 6014P-82R 6014P-8

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Chapter 7: BIOS

Adjacent Cache Line Prefetch

The CPU fetches the cache line for 64 bytes if Disabled. The CPU fetches both cache lines for 128 bytes as comprised if Enabled.

I/O Device Configuration

Access the submenu to make changes to the following settings.

KBC Clock input

This setting allows you to set the clock frequency for the Keyboard Clock. The options are 8MHz, 12 MHz and 16MHz.

Onboard COM1

This setting allows you to assign control of Onboard COM1. The options are Enabled (user defined), Disabled, and Auto (BIOS- or OS- controlled).

Base I/O Address

Select the base I/O address for COM1. The options are 3F8/IRQ4, 2F8/ IRQ3, 3E8/IRQ4 and 2E8/IRQ3.

Onboard COM2

This setting allows you to assign control of Onboard COM2. The options are Enabled (user defined), Disabled, and Auto (BIOS- or OS- controlled).

Base I/O Address

Select the base I/O address for COM2. The options are 3F8/IRQ4, 2F8/ IRQ3, 3E8/IRQ4 and 2E8/IRQ3.

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SUPER MICRO Computer 6014P-82R Adjacent Cache Line Prefetch, Device Configuration, KBC Clock input, Onboard COM1