Symmetricom XLi IEEE 1588 manual Clock Architecture, Dac

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Clock Architecture

Figures 1 and 2 on the following pages provide a simplified view of the standard XLi's clock architecture.

Aux Ref

1 PPS A 1PPS B

Code Input

Aux Ref

1,5,10 MHz

DAC

10 MHz Osc.

1PPS Timing Select

Time and Clock

Recovery

Code Input

16.384 MHz Osc. PLL

Phase Measurement

Clock DPLL

200 MHz PLL

Phase Compare

Clock Machine

Code Generation

Rate Gen

1 PPS
	1 PPS Out
Output

Code Out	Code Out
Rate Out	Rate Out

Figure 1: Functional Timing Block Diagram

XLi IEEE 1588 Clock 7

997-01510-03, Rev. C, 12/12/2006