
2 Troubleshooting Procedures
Code Beeps POST Routine Description
14h | Initialize keyboard controller |
16h | BIOS ROM checksum |
17h | Initialize cache before memory autosize |
18h | 8254 timer initialization |
1Ah | 8237 DMA controller initialization |
1Ch | Reset Programmable Interrupt Controller |
20h | Test DRAM refresh |
22h | Test 8742 Keyboard Controller |
24h | Set ES segment register to 4 GB |
26h | Enable A20 line |
28h | Autosize DRAM |
29h | Initialize POST Memory Manager |
2Ah | Clear 512 KB base RAM |
2Ch | RAM failure on address line xxxx* |
2Eh | RAM failure on data bits xxxx* of low byte of memory bus |
2Fh | Enable cache before system BIOS shadow |
30h | RAM failure on data bits xxxx* of high byte of memory bus |
32h | Test CPU |
33h | Initialize Phoenix Dispatch Manager |
36h | Warm start shut down |
38h | Shadow system BIOS ROM |
3Ah | Autosize cache |
3Ch | Advanced configuration of chipset registers |
3Dh | Load alternate registers with CMOS values |
42h | Initialize interrupt vectors |
45h | POST device initialization |
46h | |
48h | Check video configuration against CMOS |
49h | Initialize PCI bus and devices |
4Ah | Initialize all video adapters in system |
4Bh | QuietBoot start (optional) |
4Ch | Shadow video BIOS ROM |
4Eh | Display BIOS copyright notice |
50h | Display CPU type and speed |
51h | Initialize EISA board |
52h | Test keyboard |
54h | Set key click if enabled |
58h | |
59h | Initialize POST display service |
5Ah | Display prompt "Press F2 to enter SETUP" |
5Bh | Disable CPU cache |
5Ch | Test RAM between 512 and 640 KB |
60h | Test extended memory |
62h | Test extended memory address lines |
64h | Jump to UserPatch1 |
Satellite P100 Maintenance Manual | 17 |