Ampro Corporation COM 830 manual Connector Pinout, Pin Row a Row B

Page 42

Chapter 3

 

Signals and Pinout Tables

Table 3-15. Power and GND Signal Descriptions

 

 

 

 

 

 

 

 

 

 

 

 

VCC_RTC

Real-time clock circuit-power input. Nominally

P

 

 

 

 

 

+3.0V.

 

 

 

 

 

GND

Ground - DC power and signal and AC signal

P

 

 

 

 

 

return path.

 

 

 

 

 

 

All available GND connector pins shall be used

 

 

 

 

 

 

and tied to Carrier Board GND plane.

 

 

 

 

 

 

 

 

 

 

 

A-B Connector Pinout

Table 3-16. Connector A-B Pinout

Pin

Row A

Pin

Row B

Pin

Row A

Pin

Row B

A1

GND (FIXED)

B1

GND (FIXED)

A56

PCIE_TX4-

B56

PCIE_RX4-

A2

GBE0_MDI3-

B2

GBE0_ACT#

A57

GND

B57

GPO2

A3

GBE0_MDI3+

B3

LPC_FRAME#

A58

PCIE_TX3+

B58

PCIE_RX3

 

 

 

 

 

 

 

+

A4

GBE0_LINK100#

B4

LPC_AD0

A59

PCIE_TX3-

B59

PCIE_RX3-

A5

GBE0_LINK1000#

B5

LPC_AD1

A60

GND (FIXED)

B60

GND

 

 

 

 

 

 

 

(FIXED)

A6

GBE0_MDI2-

B6

LPC_AD2

A61

PCIE_TX2+

B61

PCIE_RX2

 

 

 

 

 

 

 

+

A7

GBE0_MDI2+

B7

LPC_AD3

A62

PCIE_TX2-

B62

PCIE_RX2-

A8

GBE0_LINK#

B8

LPC_DRQ0#

A63

GPI1 (*)

B63

GPO3

A9

GBE0_MDI1-

B9

LPC_DRQ1#

A64

PCIE_TX1+

B64

PCIE_RX1

 

 

 

 

 

 

 

+

A1

GBE0_MDI1+

B10

LPC_CLK

A65

PCIE_TX1-

B65

PCIE_RX1-

0

 

 

 

 

 

 

 

A11

GND (FIXED)

B11

GND (FIXED)

A66

GND

B66

WAKE0#

A1

GBE0_MDI0-

B12

PWRBTN#

A67

GPI2

B67

WAKE1#

2

 

 

 

 

 

 

 

A1

GBE0_MDI0+

B13

SMB_CK

A68

PCIE_TX0+

B68

PCIE_RX0

3

 

 

 

 

 

 

+

A1

GBE0_CTREF

B14

SMB_DAT

A69

PCIE_TX0-

B69

PCIE_RX0-

4

 

 

 

 

 

 

 

A1

SUS_S3#

B15

SMB_ALERT#

A70

GND (FIXED)

B70

GND

5

 

 

 

 

 

 

(FIXED)

A1

SATA0_TX+

B16

SATA1_TX+

A71

LVDS_A0+

B71

LVDS_B0+

6

 

 

 

 

 

 

 

A1

SATA0_TX-

B17

SATA1_TX-

A72

LVDS_A0-

B72

LVDS_B0-

7

 

 

 

 

 

 

 

A1

SUS_S4# (*)

B18

SUS_STAT#

A73

LVDS_A1+

B73

LVDS_B1+

8

 

 

 

 

 

 

 

A1

SATA0_RX+

B19

SATA1_RX+

A74

LVDS_A1-

B74

LVDS_B1-

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

36

Reference Manual

COM 830

Image 42
Contents COM Computer-On-Module Reference Manual Audience Contents Ahci RAID Bios Setup Description Appendix aAC97/Intel High Definition Audio Link Signals Descriptions List of TablesTerminology SymbolsWarranty Term DescriptionCOM Express Concept PCIElectrostatic Sensitive Device CertificationTechnical Support Lead-Free Designs RoHS COM 830 Options InformationReference Manual COM Feature List Usable Memory Mechanical DimensionsPower Supported Operating SystemsElectrical Characteristics Supply Voltage Standard PowerPower Consumption Electrostatic Sensitive DeviceProcessor Information Environmental Specifications Block Diagram Intel 82945GMHeatspreader Heatspreader Dimensions Connector Subsystems Rows A, B, C, D Primary Connector Rows a and BExpressCard Power ControlPCI Express Graphics Output VGA/CRTPower Supply Implementation Guidelines Additional FeaturesEmbedded Bios Onboard MicrocontrollerSimplified Overview of Bios Setup Data Backup Suspend to Ram Security FeaturesComparison of I/O Apic to 8259 PIC Interrupt mode Ampro Tech NotesCompatible Mode Native vs. Compatible IDE modeIntel Processor Features Native ModeProcessor Performance Control IntelThermal Management Intel Virtualization TechnologyPassive Cooling Critical Trip Point Acpi Suspend Modes and Resume EventsActive Cooling ΔP% = TC1Tn-Tn-1 + TC2Tn-TtGPI2# SMBALERT#WAKE# PME# Routing Diagram USB 2.0 Ehci Host Controller SupportDDC PciePDS Connector Signal Descriptions Gigabit Ethernet Description CommentSATA2TX+ SATA2RX+SATA2RX SATA2TXPCIE4RX+ PCIE3TX+PCIE3TX PCIE4RXUSB1+ USB0+USB0 USB1USB7 VgaredVgagrn Commen Tvdacc Biosdisable Tvdacb I2CCKPWRBTN# SysresetCBRESET# PwrokSignal Description Comment Connector Pinout Pin Row a Row BLVDSB2+ GND Fixed Rsvd EF+ BIOSDISABLE#LVDSA2+ LVDSA2EXCD0PERST# SYSRESET#EXCD1PERST# EXCD1CPPE#PCISTOP# PCIRESET#PCITRDY# PciparIDEIOR# IderesetPEGENABLE# IdereqSDVOBGRN+ SDVOBRED+Pcie Sdvobred Pcie SdvobgrnType TYPE2# TYPE1# TYPE0#Pin Row C Row D PCIAD16 PEGRX12+PEGTX12+ PEGRX12Audio Serial Data Out This signal Boot Strap SignalsSignal Description of Boot Strap Signal AC ’97/Intel High DefinitionAddress Assignment BiosSystem Resources System Memory MapAddress hex Size Available Description 0CFC 0CFFInterrupt Request IRQ Lines Available Typical Interrupt Source Connected to PinPIC PCI Configuration Space Map IRQ14IRQ15 29. PCI Configuration Space Map Mode PCI Interrupt Routing MapAzalia Native BusSM Bus PCI Bus Masters²C Bus Native Root PortBoot Selection Popup Entering the Bios Setup ProgramSetup Menu and Navigation Manufacturer Default SettingsBios ID Main Setup ScreenFeature Options Description ESCAdvanced Setup Acpi Configuration Submenu YesAcpi Win XP Watchdog Acpi Event restart configuration PCI Configuration SubmenuPCI IRQ Resource Exclusion Submenu Graphics Configuration SubmenuEnabled, 8MB PCI Interrupt Routing SubmenuLFP SDVO-B SDVO-C CRT + SdvoCRT + LFP LFP SDVO-C SDVO-BCRT Lvds PAL Bios Secam SMPTE240MDVI NtscCPU Configuration Submenu Bios Setup Description Chipset Configuration Submenu IoapicApic Acpi SCI IRQ Interface Configuration Submenu 3F8/IRQ4 SIO Winbond W83627 ConfigurationDisabled 2F8/IRQ3RAID Clock ConfigurationIDE Configuration Submenu IDEHost&Device A.R.T Primary/Secondary IDE Master/Slave SubmenuAtapi Cdrom CD/DVDEnabled USB Configuration Submenu HiSpeedKeyboard/Mouse Configuration Submenu USB Mass Storage Device Configuration SubmenuCD-ROM COM2 Remote Access Configuration SubmenuBios Post AnsiHardware Monitoring Submenu +5VSBVbat Watchdog Configuration Submenu NMIBoot Setup Boot Device Priority USB CdromPCI RAID Boot Settings Configuration Security Setup Security Settings Hard Disk SecurityPower Setup Hard Disk Security User PasswordAPM Additional Bios Features Updating the BiosBios Recovery Bios Security Features Hard Disk Security FeaturesSerial Port and Console Redirection Industry Specifications Specification LinkLPC Reference Manual COM Appendix a Technical Support Method Contact InformationAppendix a