Ampro Corporation COM 830 manual Ddc, Pcie, Pds

Page 31

Chapter 3 Signals and Pinout Tables

The following section describes the signals found on COM Express™ Type II connectors used for Ampro modules.

The table below describes the terminology used in this section for the Signal Description tables. The PU/PD column indicates if a COM Express internal pull-up or pull-down resistor has been used. If the field entry area in this column for the signal is empty, then no pull-up or pull-down resistor has been implemented.

The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at a high voltage level.

Table 3-1. Signal Tables Terminology Descriptions

Term

Description

PU

COM Express internally implemented Pull up resistor

 

 

PD

COM Express internally implemented Pull down resistor

 

 

I/O 3.3V

Bi-directional signal 3.3V tolerant

 

 

I/O 5V

Bi-directional signal 5V tolerant

 

 

I 3.3V

Input 3.3V tolerant

 

 

I 5V

Input 5V tolerant

 

 

I/O 3.3VSB

Input 3.3V tolerant active in standby state

 

 

O 3.3V

Output 3.3V signal level

 

 

O 5V

Output 5V signal level

 

 

OD

Open drain output

 

 

P

Power Input/Output

 

 

DDC

Display Data Channel

 

 

PCIE

In compliance with PCI Express Base Specification, Revision 1.0a

 

 

SATA

In compliance with Serial ATA specification, Revision 1.0a

 

 

REF

Reference voltage output. May be sourced from a module power plane.

 

 

PDS

Pull-down strap. A module output pin that is either tied to GND or is not connected.

 

Used to signal module capabilities (pinout type) to the Carrier Board.

 

 

COM 830

Reference Manual

25

Image 31
Contents COM Computer-On-Module Reference Manual Audience Contents Ahci RAID Appendix a Bios Setup DescriptionList of Tables AC97/Intel High Definition Audio Link Signals DescriptionsTerm Description SymbolsWarranty TerminologyPCI COM Express ConceptCOM 830 Options Information CertificationTechnical Support Lead-Free Designs RoHS Electrostatic Sensitive DeviceReference Manual COM Feature List Supported Operating Systems Mechanical DimensionsPower Usable MemoryElectrostatic Sensitive Device Supply Voltage Standard PowerPower Consumption Electrical CharacteristicsProcessor Information Environmental Specifications Intel 82945GM Block DiagramHeatspreader Heatspreader Dimensions Primary Connector Rows a and B Connector Subsystems Rows A, B, C, DGraphics Output VGA/CRT Power ControlPCI Express ExpressCardAdditional Features Power Supply Implementation GuidelinesOnboard Microcontroller Embedded BiosSimplified Overview of Bios Setup Data Backup Ampro Tech Notes Security FeaturesComparison of I/O Apic to 8259 PIC Interrupt mode Suspend to RamNative Mode Native vs. Compatible IDE modeIntel Processor Features Compatible ModeIntel Processor Performance ControlIntel Virtualization Technology Thermal ManagementPassive Cooling ΔP% = TC1Tn-Tn-1 + TC2Tn-Tt Acpi Suspend Modes and Resume Events Active Cooling Critical Trip PointSMBALERT# GPI2#WAKE# PME# USB 2.0 Ehci Host Controller Support Routing DiagramPcie DDCPDS Connector Signal Descriptions Comment Gigabit Ethernet DescriptionSATA2TX SATA2RX+SATA2RX SATA2TX+PCIE4RX PCIE3TX+PCIE3TX PCIE4RX+USB1 USB0+USB0 USB1+Vgared USB7Vgagrn Commen I2CCK BiosdisableTvdacb TvdaccPwrok SysresetCBRESET# PWRBTN#Signal Description Comment Pin Row a Row B Connector PinoutLVDSA2 Rsvd EF+ BIOSDISABLE#LVDSA2+ LVDSB2+ GND FixedEXCD1CPPE# SYSRESET#EXCD1PERST# EXCD0PERST#Pcipar PCIRESET#PCITRDY# PCISTOP#Idereq IderesetPEGENABLE# IDEIOR#Pcie Sdvobgrn SDVOBRED+Pcie Sdvobred SDVOBGRN+TYPE2# TYPE1# TYPE0# TypePin Row C Row D PEGRX12 PEGRX12+PEGTX12+ PCIAD16AC ’97/Intel High Definition Boot Strap SignalsSignal Description of Boot Strap Signal Audio Serial Data Out This signalSystem Memory Map BiosSystem Resources Address Assignment0CFC 0CFF Address hex Size Available DescriptionAvailable Typical Interrupt Source Connected to Pin Interrupt Request IRQ LinesPIC IRQ14 PCI Configuration Space MapIRQ15 29. PCI Configuration Space Map Native Bus PCI Interrupt Routing MapAzalia ModeNative Root Port PCI Bus Masters²C Bus SM BusManufacturer Default Settings Entering the Bios Setup ProgramSetup Menu and Navigation Boot Selection PopupESC Main Setup ScreenFeature Options Description Bios IDAdvanced Setup Yes Acpi Configuration SubmenuAcpi PCI Configuration Submenu Win XP Watchdog Acpi Event restart configurationPCI Interrupt Routing Submenu Graphics Configuration SubmenuEnabled, 8MB PCI IRQ Resource Exclusion SubmenuLFP SDVO-C SDVO-B CRT + SdvoCRT + LFP LFP SDVO-B SDVO-CNtsc PAL Bios Secam SMPTE240MDVI CRT LvdsCPU Configuration Submenu Bios Setup Description Ioapic Chipset Configuration SubmenuApic Acpi SCI IRQ Interface Configuration Submenu 2F8/IRQ3 SIO Winbond W83627 ConfigurationDisabled 3F8/IRQ4IDE Clock ConfigurationIDE Configuration Submenu RAIDHost&Device CD/DVD Primary/Secondary IDE Master/Slave SubmenuAtapi Cdrom A.R.TEnabled HiSpeed USB Configuration SubmenuUSB Mass Storage Device Configuration Submenu Keyboard/Mouse Configuration SubmenuCD-ROM Ansi Remote Access Configuration SubmenuBios Post COM2+5VSB Hardware Monitoring SubmenuVbat NMI Watchdog Configuration SubmenuBoot Setup USB Cdrom Boot Device PriorityPCI RAID Boot Settings Configuration Security Setup Hard Disk Security Security SettingsHard Disk Security User Password Power SetupAPM Updating the Bios Additional Bios FeaturesBios Recovery Hard Disk Security Features Bios Security FeaturesSerial Port and Console Redirection Specification Link Industry SpecificationsLPC Reference Manual COM Method Contact Information Appendix a Technical SupportAppendix a