Ampro Corporation COM 830 manual PCI Configuration Space Map, IRQ14, IRQ15

Page 55

Chapter 3

 

 

Signals and Pinout Tables

Table 3-28. IRQ Lines in APIC mode (Continued)

 

 

 

 

 

 

 

 

 

9

Note 2

Generic

IRQ9 via SERIRQ, option for SCI

 

 

10

Yes

 

IRQ10 via SERIRQ

 

 

11

Yes

 

IRQ11 via SERIRQ

 

 

12

Yes

 

IRQ12 via SERIRQ

 

 

13

No

Math processor

Not applicable

 

 

14

Note 1

IDE Controller 0 (IDE0) /

IRQ14

 

 

 

 

Generic

 

 

 

15

Note 1

IDE Controller 1 (IDE1) /

IRQ15

 

 

 

 

Generic

 

 

 

16

No

 

PIRQA, Integrated VGA Controller, PCI

 

 

 

 

 

Express Root Port 1, Intel High

 

 

 

 

 

Definition Audio Controller (Azalia),

 

 

 

 

 

UHCI Host Controller 3

 

 

17

No

 

PIRQB, AC'97 Audio, PCI Express Root

 

 

 

 

 

Port 2, PCI Express Root Port 6, onboard

 

 

 

 

 

Gigabit LAN Controller

 

 

18

No

 

PIRQC, Parallel ATA Controller in

 

 

 

 

 

enhanced/native mode, UHCI Host

 

 

 

 

 

Controller 2, PCI Express Root Port 3

 

 

19

No

 

PIRQD, Serial ATA controller in

 

 

 

 

 

enhanced/native mode, UHCI Host

 

 

 

 

 

Controller 1, SMBus Controller, PCI

 

 

 

 

 

Express Root Port 4

 

 

20

Yes

 

PIRQE, PCI Bus INTD, option for SCI

 

 

21

Yes

 

PIRQF, PCI Bus INTA

 

 

22

Yes

 

PIRQG, PCI Bus INTB

 

 

23

Yes

 

PIRQH, PCI Bus INTC, UHCI Host

 

 

 

 

 

Controller 0, EHCI Host Controller

 

 

 

 

 

 

 

In APIC mode, the PCI bus interrupt lines are connected with IRQ 20, 21, 22 and 23.

NOTE If the ATA/IDE configuration is set to enhanced mode in BIOS setup (serial ATA and parallel ATA native mode operation), IRQ14 and 15 are free for PCI/LPC bus.

In ACPI mode, IRQ9 is used for the SCI (System Control Interrupt). The SCI can be shared with a PCI interrupt line.

PCI Configuration Space Map

Table 3-29. PCI Configuration Space Map

Bus Number

Device Number

Function Number

PCI Interrupt

Description

(hex)

(hex)

(hex)

Routing

 

00h

00h

00h

N.A.

Host Bridge

00h

01h

00h

Internal

PCI Express Graphics

 

 

 

 

Root Port

00h

02h

00h

Internal

VGA Graphics

 

 

 

 

 

COM 830

Reference Manual

49

Image 55
Contents COM Computer-On-Module Reference Manual Audience Contents Ahci RAID Appendix a Bios Setup DescriptionList of Tables AC97/Intel High Definition Audio Link Signals DescriptionsTerm Description SymbolsWarranty TerminologyPCI COM Express ConceptCOM 830 Options Information CertificationTechnical Support Lead-Free Designs RoHS Electrostatic Sensitive DeviceReference Manual COM Feature List Supported Operating Systems Mechanical DimensionsPower Usable MemoryElectrostatic Sensitive Device Supply Voltage Standard PowerPower Consumption Electrical CharacteristicsProcessor Information Environmental Specifications Intel 82945GM Block DiagramHeatspreader Heatspreader Dimensions Primary Connector Rows a and B Connector Subsystems Rows A, B, C, DGraphics Output VGA/CRT Power ControlPCI Express ExpressCardAdditional Features Power Supply Implementation GuidelinesOnboard Microcontroller Embedded BiosSimplified Overview of Bios Setup Data Backup Ampro Tech Notes Security FeaturesComparison of I/O Apic to 8259 PIC Interrupt mode Suspend to RamNative Mode Native vs. Compatible IDE modeIntel Processor Features Compatible ModeIntel Processor Performance ControlIntel Virtualization Technology Thermal ManagementPassive Cooling ΔP% = TC1Tn-Tn-1 + TC2Tn-Tt Acpi Suspend Modes and Resume EventsActive Cooling Critical Trip PointSMBALERT# GPI2#WAKE# PME# USB 2.0 Ehci Host Controller Support Routing DiagramPcie DDCPDS Connector Signal Descriptions Comment Gigabit Ethernet DescriptionSATA2TX SATA2RX+SATA2RX SATA2TX+PCIE4RX PCIE3TX+PCIE3TX PCIE4RX+USB1 USB0+USB0 USB1+Vgared USB7Vgagrn Commen I2CCK BiosdisableTvdacb TvdaccPwrok SysresetCBRESET# PWRBTN#Signal Description Comment Pin Row a Row B Connector PinoutLVDSA2 Rsvd EF+ BIOSDISABLE#LVDSA2+ LVDSB2+ GND FixedEXCD1CPPE# SYSRESET#EXCD1PERST# EXCD0PERST#Pcipar PCIRESET#PCITRDY# PCISTOP#Idereq IderesetPEGENABLE# IDEIOR#Pcie Sdvobgrn SDVOBRED+Pcie Sdvobred SDVOBGRN+TYPE2# TYPE1# TYPE0# TypePin Row C Row D PEGRX12 PEGRX12+PEGTX12+ PCIAD16AC ’97/Intel High Definition Boot Strap SignalsSignal Description of Boot Strap Signal Audio Serial Data Out This signal System Memory Map Bios System Resources Address Assignment0CFC 0CFF Address hex Size Available DescriptionAvailable Typical Interrupt Source Connected to Pin Interrupt Request IRQ LinesPIC IRQ14 PCI Configuration Space MapIRQ15 29. PCI Configuration Space Map Native Bus PCI Interrupt Routing MapAzalia ModeNative Root Port PCI Bus Masters²C Bus SM BusManufacturer Default Settings Entering the Bios Setup ProgramSetup Menu and Navigation Boot Selection PopupESC Main Setup ScreenFeature Options Description Bios IDAdvanced Setup Yes Acpi Configuration SubmenuAcpi PCI Configuration Submenu Win XP Watchdog Acpi Event restart configurationPCI Interrupt Routing Submenu Graphics Configuration SubmenuEnabled, 8MB PCI IRQ Resource Exclusion SubmenuLFP SDVO-C SDVO-B CRT + SdvoCRT + LFP LFP SDVO-B SDVO-CNtsc PAL Bios Secam SMPTE240MDVI CRT LvdsCPU Configuration Submenu Bios Setup Description Ioapic Chipset Configuration SubmenuApic Acpi SCI IRQ Interface Configuration Submenu 2F8/IRQ3 SIO Winbond W83627 ConfigurationDisabled 3F8/IRQ4IDE Clock ConfigurationIDE Configuration Submenu RAIDHost&Device CD/DVD Primary/Secondary IDE Master/Slave SubmenuAtapi Cdrom A.R.TEnabled HiSpeed USB Configuration SubmenuUSB Mass Storage Device Configuration Submenu Keyboard/Mouse Configuration SubmenuCD-ROM Ansi Remote Access Configuration SubmenuBios Post COM2+5VSB Hardware Monitoring SubmenuVbat NMI Watchdog Configuration SubmenuBoot Setup USB Cdrom Boot Device PriorityPCI RAID Boot Settings Configuration Security Setup Hard Disk Security Security SettingsHard Disk Security User Password Power SetupAPM Updating the Bios Additional Bios FeaturesBios Recovery Hard Disk Security Features Bios Security FeaturesSerial Port and Console Redirection Specification Link Industry SpecificationsLPC Reference Manual COM Method Contact Information Appendix a Technical SupportAppendix a