Chapter 3 |
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| TV_DAC_B | TVDAC Channel B Output supports the |
| O | PD 150R |
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| following: Composite video: not used |
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| Component video: Luminance (Y) analog |
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| TV_DAC_C | TVDAC Channel C Output supports the |
| O | PD 150R |
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| following: Composite video: not used |
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| Component: Chrominance (Pr) analog |
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| Signal | Description |
| I/O | PU/PD | Comment | ||
| I2C_CK | General purpose I²C port clock output |
| O 3.3V | PU 4k7 |
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| 3.3V |
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| I2C_DAT | General purpose I²C port data I/O line |
| I/O | PU 4k7 |
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| 3.3V | 3.3V |
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| SPKR | Output for audio enunciator, the "speaker" in |
| O 3.3V |
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| strap signal | |
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| (see note 1 | |
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| BIOS_DISABLE | Module BIOS disable input. Pull low to disable | I 3.3V | PU 4k7 |
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| # | module BIOS. Used to allow |
| 3.3V |
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| WDT | Output indicating that a watchdog |
| I 3.3V | PU 10k | This signal | ||
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| 3.3V | is not | ||
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| (see note 2 | |
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| KBD_RST# | Input to module from (optional) external |
| I | PU 10k |
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| keyboard controller that can force a reset. |
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| 3.3V |
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| Pulled high on the module. This is a legacy |
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| artifact of the |
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| KBD_A20GATE | Input to module from (optional) external |
| I | PU 10k |
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| keyboard controller that can be used to control |
| 3.3V |
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| the CPU A20 gate line. The A20GATE restricts |
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| the memory access to the bottom megabyte and |
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| is a legacy artifact of the |
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NOTE Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module.
For more information about this signal, please visit Ask an Expert on the Ampro web site.
COM 830 | Reference Manual | 33 |