Chapter 4 | BIOS Setup Description |
Chipset Configuration Submenu
Feature
Options
Description
Memory Hole | Disabled | Enable or disable the memory hole between 15MB | |
| and 16MB. If enabled, accesses to this range are | ||
| forwarded to the LPC / PCI bus. | ||
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Chipset Thermal | Disabled | This enables or disables chipset thermal throttling. | |
Throttling | Enabled |
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IOAPIC | Disabled | Enable / Disable | |
| Enabled |
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APIC ACPI SCI IRQ | Disabled | If set to Disabled IRQ9 is used for the SCI. | |
| Enabled | If set to Enabled IRQ20 is used for the SCI. | |
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C4 On C3 | Disabled | If enabled the CPU is put to C4 state, when the ACPI | |
| Enabled | OS initiates a transition to C3, for additional power | |
| saving at “Desktop Idle Mode”. | ||
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Active State Power | Disabled | Enable or disable PCI Express L0s and L1 link power | |
Management | Enabled | states. |
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PCIE Port 0 | Auto | Enable or disable | PCI Express port. |
| Enabled |
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| Disabled |
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PCIE Port 1 | Auto | Enable or disable | PCI Express port. |
| Enabled |
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| Disabled |
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PCIE Port 2 | Auto | Enable or disable | PCI Express port. |
| Enabled |
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| Disabled |
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PCIE Port 3 | Auto | Enable or disable | PCI Express port. |
| Enabled |
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| Disabled |
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PCIE Port 4 | Auto | Enable or disable | PCI Express port. |
| Enabled |
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| Disabled |
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PCIE High Priority | Disabled | Enable PCI Express high priority port for isochronous | |
Port | Port 0 | data transfers. |
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| Port 1 |
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| Port 2 |
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| Port 3 |
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| Port 4 |
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PCIE Port 0 IOxAPIC | Disabled | Enable support for IOAPIC behind PCI Express port. | |
Enable | Enabled |
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COM 830 | Reference Manual | 63 |