Ampro Corporation COM 830 Sdvobred+, Pcie Sdvobred, Sdvobgrn+, Pcie Sdvobgrn, Sdvobblu+, Sdvobck+

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Chapter 3Signals and Pinout Tables

Table 3-20. SDVO Signal Descriptions

Signal

Description

I/O

PU/PD

Comment

SDVOB_RED+

Serial Digital Video B red output

O PCIE

 

 

SDVOB_RED-

differential pair Multiplexed with

 

 

 

 

PEG_TX[0]+ and PEG_TX[0]- pair

 

 

 

SDVOB_GRN+

Serial Digital Video B green output

O PCIE

 

 

SDVOB_GRN-

differential pair Multiplexed with

 

 

 

 

PEG_TX[1]+ and PEG_TX[1]-

 

 

 

SDVOB_BLU+

Serial Digital Video B blue output

O PCIE

 

 

SDVOB_BLU-

differential pair Multiplexed with

 

 

 

 

PEG_TX[2]+ and PEG_TX[2]-

 

 

 

SDVOB_CK+

Serial Digital Video B clock output

O PCIE

 

 

SDVOB_CK-

differential pair. Multiplexed with

 

 

 

 

PEG_TX[3]+ and PEG_TX[3]-

 

 

 

SDVOB_INT+

Serial Digital Video B interrupt input

I PCIE

 

 

SDVOB_INT-

differential pair. Multiplexed with

 

 

 

 

PEG_RX[1]+ and PEG_RX[1]-

 

 

 

SDVOC_RED+

Serial Digital Video C red output

O PCIE

 

 

SDVOC_RED-

differential pair. Multiplexed with

 

 

 

 

PEG_TX[4]+ and PEG_TX[4]-

 

 

 

SDVOC_GRN+

Serial Digital Video C green output

O PCIE

 

 

SDVOC_GRN-

differential pair. Multiplexed with

 

 

 

 

PEG_TX[5]+ and PEG_TX[5]-

 

 

 

SDVOC_BLU+

Serial Digital Video C blue output

O PCIE

 

 

SDVOC_BLU-

differential pair. Multiplexed with

 

 

 

 

PEG_TX[6]+ and PEG_TX[6]-

 

 

 

SDVOC_CK+

Serial Digital Video C clock output

O PCIE

 

 

SDVOC_CK-

differential pair. Multiplexed with

 

 

 

 

PEG_TX[7]+ and PEG_TX[7]-

 

 

 

SDVOC_INT+

Serial Digital Video C interrupt input

I PCIE

 

 

SDVOC_INT-

differential pair. Multiplexed with

 

 

 

 

PEG_RX[5]+ and PEG_RX[5]-

 

 

 

SDVO_TVCLKIN+

Serial Digital Video TVOUT

I PCIE

 

 

SDVO_TVCLKIN-

synchronization clock input

 

 

 

 

differential pair. Multiplexed with

 

 

 

 

PEG_RX[0]+ and PEG_RX[0]-

 

 

 

SDVO_FLDSTALL+

Serial Digital Video Field Stall input

I PCIE

 

 

SDVO_FLDSTALL-

differential pair. Multiplexed with

 

 

 

 

PEG_RX[2]+ and PEG_RX[2]-

 

 

 

SDVO_I2C_CK

SDVO I²C clock line to set up SDVO

O 2.5V

 

 

(SDVO_CLK)

peripherals.

 

 

 

 

 

 

 

 

 

 

 

 

SDVO_I2C_DAT

SDVO I²C data line to set up SDVO

I/O OD

 

SDVO_I2C_

(SDVO_DATA)

peripherals.

2.5V

 

DAT is a

 

 

 

boot strap

 

 

 

 

 

 

 

 

signal (see

 

 

 

 

note below)

 

 

 

 

 

COM 830

Reference Manual

41

Page 46 Page 48
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Page 46 Page 48
Contents COM Computer-On-Module Reference Manual Audience Contents Ahci RAID Appendix a Bios Setup DescriptionList of Tables AC97/Intel High Definition Audio Link Signals DescriptionsTerm Description SymbolsWarranty TerminologyPCI COM Express ConceptCOM 830 Options Information CertificationTechnical Support Lead-Free Designs RoHS Electrostatic Sensitive DeviceReference Manual COM Feature List Supported Operating Systems Mechanical DimensionsPower Usable MemoryElectrostatic Sensitive Device Supply Voltage Standard PowerPower Consumption Electrical CharacteristicsProcessor Information Environmental Specifications Intel 82945GM Block DiagramHeatspreader Heatspreader Dimensions Primary Connector Rows a and B Connector Subsystems Rows A, B, C, DGraphics Output VGA/CRT Power ControlPCI Express ExpressCardAdditional Features Power Supply Implementation GuidelinesOnboard Microcontroller Embedded BiosSimplified Overview of Bios Setup Data Backup Ampro Tech Notes Security FeaturesComparison of I/O Apic to 8259 PIC Interrupt mode Suspend to RamNative Mode Native vs. Compatible IDE modeIntel Processor Features Compatible ModeIntel Processor Performance ControlPassive Cooling Thermal ManagementIntel Virtualization Technology ΔP% = TC1Tn-Tn-1 + TC2Tn-Tt Acpi Suspend Modes and Resume EventsActive Cooling Critical Trip PointWAKE# PME# GPI2#SMBALERT# USB 2.0 Ehci Host Controller Support Routing DiagramPDS DDCPcie Connector Signal Descriptions Comment Gigabit Ethernet DescriptionSATA2TX SATA2RX+SATA2RX SATA2TX+PCIE4RX PCIE3TX+PCIE3TX PCIE4RX+USB1 USB0+USB0 USB1+Vgagrn USB7Vgared Commen I2CCK BiosdisableTvdacb TvdaccPwrok SysresetCBRESET# PWRBTN#Signal Description Comment Pin Row a Row B Connector PinoutLVDSA2 Rsvd EF+ BIOSDISABLE#LVDSA2+ LVDSB2+ GND FixedEXCD1CPPE# SYSRESET#EXCD1PERST# EXCD0PERST#Pcipar PCIRESET#PCITRDY# PCISTOP#Idereq IderesetPEGENABLE# IDEIOR#Pcie Sdvobgrn SDVOBRED+Pcie Sdvobred SDVOBGRN+TYPE2# TYPE1# TYPE0# TypePin Row C Row D PEGRX12 PEGRX12+PEGTX12+ PCIAD16AC ’97/Intel High Definition Boot Strap SignalsSignal Description of Boot Strap Signal Audio Serial Data Out This signalSystem Memory Map BiosSystem Resources Address Assignment0CFC 0CFF Address hex Size Available DescriptionPIC Interrupt Request IRQ LinesAvailable Typical Interrupt Source Connected to Pin IRQ15 PCI Configuration Space MapIRQ14 29. PCI Configuration Space Map Native Bus PCI Interrupt Routing MapAzalia ModeNative Root Port PCI Bus Masters²C Bus SM BusManufacturer Default Settings Entering the Bios Setup ProgramSetup Menu and Navigation Boot Selection PopupESC Main Setup ScreenFeature Options Description Bios IDAdvanced Setup Acpi Acpi Configuration SubmenuYes PCI Configuration Submenu Win XP Watchdog Acpi Event restart configurationPCI Interrupt Routing Submenu Graphics Configuration SubmenuEnabled, 8MB PCI IRQ Resource Exclusion SubmenuLFP SDVO-C SDVO-B CRT + SdvoCRT + LFP LFP SDVO-B SDVO-CNtsc PAL Bios Secam SMPTE240MDVI CRT LvdsCPU Configuration Submenu Bios Setup Description Apic Acpi SCI IRQ Chipset Configuration SubmenuIoapic Interface Configuration Submenu 2F8/IRQ3 SIO Winbond W83627 ConfigurationDisabled 3F8/IRQ4IDE Clock ConfigurationIDE Configuration Submenu RAIDHost&Device CD/DVD Primary/Secondary IDE Master/Slave SubmenuAtapi Cdrom A.R.TEnabled HiSpeed USB Configuration SubmenuCD-ROM Keyboard/Mouse Configuration SubmenuUSB Mass Storage Device Configuration Submenu Ansi Remote Access Configuration SubmenuBios Post COM2Vbat Hardware Monitoring Submenu+5VSB NMI Watchdog Configuration SubmenuBoot Setup PCI RAID Boot Device PriorityUSB Cdrom Boot Settings Configuration Security Setup Hard Disk Security Security SettingsAPM Power SetupHard Disk Security User Password Bios Recovery Additional Bios FeaturesUpdating the Bios Serial Port and Console Redirection Bios Security FeaturesHard Disk Security Features LPC Industry SpecificationsSpecification Link Reference Manual COM Method Contact Information Appendix a Technical SupportAppendix a
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