Ampro Corporation COM 830 Pcitrdy#, Pcistop#, Pcipar, Pciperr#, Pcireset#, Pcilock#, Pciserr#

Page 45

Chapter 3

 

 

 

 

 

 

Signals and Pinout Tables

Table 3-17. PCI Signal Descriptions (Continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI_TRDY#

 

PCI bus Target Ready control line, active low

I/O

 

PU 8k2

 

 

 

 

 

 

 

 

3.3V

 

3.3V

 

 

 

 

PCI_STOP#

 

PCI bus STOP control line, active low, driven

I/O

 

PU 8k2

 

 

 

 

 

 

 

by cycle initiator

3.3V

 

3.3V

 

 

 

 

PCI_PAR

 

PCI bus parity

I/O

 

 

 

 

 

 

 

 

 

 

 

3.3V

 

 

 

 

 

 

 

PCI_PERR#

 

Parity Error: An external PCI device drives

I/O

 

PU 8k2

 

 

 

 

 

 

 

PERR# when it receives data that has a parity

3.3V

 

3.3V

 

 

 

 

 

 

 

error.

 

 

 

 

 

 

 

 

 

PCI_REQ[0:3]#

 

PCI bus master request input lines, active low.

I 3.3V

 

PU 8k2

 

 

 

 

 

 

 

 

 

 

 

3.3V

 

 

 

 

PCI_GNT[0:3]#

 

PCI bus master grant output lines, active low.

O 3.3V

 

 

 

 

 

 

 

PCI_RESET#

 

PCI Reset output, active low.

O 3.3V

 

 

 

 

 

 

 

PCI_LOCK#

 

PCI Lock control line, active low.

I/O

 

PU 8k2

 

 

 

 

 

 

 

 

3.3V

 

3.3V

 

 

 

 

PCI_SERR#

 

System Error: SERR# may be pulsed active

I/O

 

PU 8k2

 

 

 

 

 

 

 

by any PCI device that detects a system error

3.3V

 

3.3V

 

 

 

 

 

 

 

condition.

 

 

 

 

 

 

 

 

 

PCI_PME#

 

PCI Power Management Event: PCI

I

 

PU 10k

 

 

 

 

 

 

 

peripherals drive PME# to wake system from

3.3VS

 

3.3VSB

 

 

 

 

 

 

 

low-power states S1–S5.

B

 

 

 

 

 

 

 

PCI_CLKRUN#

 

Bidirectional pin used to support PCI clock

I/O

 

PU 8k2

 

 

 

 

 

 

 

run protocol for mobile systems.

3.3V

 

3.3V

 

 

 

 

PCI_IRQ[A:D]#

 

PCI interrupt request lines.

I 3.3V

 

PU 8k2

 

 

 

 

 

 

 

 

 

 

 

3.3V

 

 

 

 

PCI_CLK

 

PCI 33MHz clock output.

O 3.3V

 

 

 

 

 

 

 

PCI_M66EN

 

Module input signal indicates whether an

I

 

 

 

Not

 

 

 

 

 

off-module PCI device is capable of 66MHz

 

 

 

 

 

connected

 

 

 

 

 

operation. Pulled to GND by Carrier Board

 

 

 

 

 

 

 

 

 

 

 

 

device or by Slot Card if the devices are NOT

 

 

 

 

 

 

 

 

 

 

 

 

capable of 66MHz operation.

 

 

 

 

 

 

 

 

 

 

 

 

If the module is not capable of supporting

 

 

 

 

 

 

 

 

 

 

 

 

66MHz PCI operation, this input may be a

 

 

 

 

 

 

 

 

 

 

 

 

no-connect on the module.

 

 

 

 

 

 

 

 

 

 

 

 

If the module is capable of supporting 66MHz

 

 

 

 

 

 

 

 

 

 

 

 

PCI operation, and if this input is held low by

 

 

 

 

 

 

 

 

 

 

 

 

the Carrier Board, the module PCI interface

 

 

 

 

 

 

 

 

 

 

 

 

shall operate at 33MHz.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 3-18. IDE Signal Descriptions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDE

 

Description

 

I/O

 

PU/PD

Comment

 

 

IDE_D[0:15]

Bidirectional data to / from IDE device.

 

I/O

 

 

 

 

 

 

 

 

 

 

 

3.3V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDE_A[0:2]

 

Address lines to IDE device.

 

O 3.3V

 

 

 

 

 

 

IDE_IOW#

 

I/O write line to IDE device. Data latched on

 

O 3.3V

 

 

 

 

 

 

 

 

trailing (rising) edge.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COM 830

Reference Manual

39

Image 45
Contents COM Computer-On-Module Reference Manual Audience Contents Ahci RAID Appendix a Bios Setup DescriptionList of Tables AC97/Intel High Definition Audio Link Signals DescriptionsWarranty SymbolsTerminology Term DescriptionPCI COM Express ConceptTechnical Support Lead-Free Designs RoHS CertificationElectrostatic Sensitive Device COM 830 Options InformationReference Manual COM Feature List Power Mechanical DimensionsUsable Memory Supported Operating SystemsPower Consumption Supply Voltage Standard PowerElectrical Characteristics Electrostatic Sensitive DeviceProcessor Information Environmental Specifications Intel 82945GM Block DiagramHeatspreader Heatspreader Dimensions Primary Connector Rows a and B Connector Subsystems Rows A, B, C, DPCI Express Power ControlExpressCard Graphics Output VGA/CRTAdditional Features Power Supply Implementation GuidelinesOnboard Microcontroller Embedded BiosSimplified Overview of Bios Setup Data Backup Comparison of I/O Apic to 8259 PIC Interrupt mode Security FeaturesSuspend to Ram Ampro Tech NotesIntel Processor Features Native vs. Compatible IDE modeCompatible Mode Native ModeIntel Processor Performance ControlThermal Management Intel Virtualization TechnologyPassive Cooling Active Cooling Acpi Suspend Modes and Resume EventsCritical Trip Point ΔP% = TC1Tn-Tn-1 + TC2Tn-TtGPI2# SMBALERT#WAKE# PME# USB 2.0 Ehci Host Controller Support Routing DiagramDDC PciePDS Connector Signal Descriptions Comment Gigabit Ethernet DescriptionSATA2RX SATA2RX+SATA2TX+ SATA2TXPCIE3TX PCIE3TX+PCIE4RX+ PCIE4RXUSB0 USB0+USB1+ USB1USB7 VgaredVgagrn Commen Tvdacb BiosdisableTvdacc I2CCKCBRESET# SysresetPWRBTN# PwrokSignal Description Comment Pin Row a Row B Connector PinoutLVDSA2+ Rsvd EF+ BIOSDISABLE#LVDSB2+ GND Fixed LVDSA2EXCD1PERST# SYSRESET#EXCD0PERST# EXCD1CPPE#PCITRDY# PCIRESET#PCISTOP# PciparPEGENABLE# IderesetIDEIOR# IdereqPcie Sdvobred SDVOBRED+SDVOBGRN+ Pcie SdvobgrnTYPE2# TYPE1# TYPE0# TypePin Row C Row D PEGTX12+ PEGRX12+PCIAD16 PEGRX12Signal Description of Boot Strap Signal Boot Strap SignalsAudio Serial Data Out This signal AC ’97/Intel High DefinitionSystem Resources BiosAddress Assignment System Memory Map0CFC 0CFF Address hex Size Available DescriptionInterrupt Request IRQ Lines Available Typical Interrupt Source Connected to PinPIC PCI Configuration Space Map IRQ14IRQ15 29. PCI Configuration Space Map Azalia PCI Interrupt Routing MapMode Native Bus²C Bus PCI Bus MastersSM Bus Native Root PortSetup Menu and Navigation Entering the Bios Setup ProgramBoot Selection Popup Manufacturer Default SettingsFeature Options Description Main Setup ScreenBios ID ESCAdvanced Setup Acpi Configuration Submenu YesAcpi PCI Configuration Submenu Win XP Watchdog Acpi Event restart configurationEnabled, 8MB Graphics Configuration SubmenuPCI IRQ Resource Exclusion Submenu PCI Interrupt Routing SubmenuCRT + LFP CRT + SdvoLFP SDVO-B SDVO-C LFP SDVO-C SDVO-BDVI PAL Bios Secam SMPTE240MCRT Lvds NtscCPU Configuration Submenu Bios Setup Description Chipset Configuration Submenu IoapicApic Acpi SCI IRQ Interface Configuration Submenu Disabled SIO Winbond W83627 Configuration3F8/IRQ4 2F8/IRQ3IDE Configuration Submenu Clock ConfigurationRAID IDEHost&Device Atapi Cdrom Primary/Secondary IDE Master/Slave SubmenuA.R.T CD/DVDEnabled HiSpeed USB Configuration SubmenuKeyboard/Mouse Configuration Submenu USB Mass Storage Device Configuration SubmenuCD-ROM Bios Post Remote Access Configuration SubmenuCOM2 AnsiHardware Monitoring Submenu +5VSBVbat NMI Watchdog Configuration SubmenuBoot Setup Boot Device Priority USB CdromPCI RAID Boot Settings Configuration Security Setup Hard Disk Security Security SettingsPower Setup Hard Disk Security User PasswordAPM Additional Bios Features Updating the BiosBios Recovery Bios Security Features Hard Disk Security FeaturesSerial Port and Console Redirection Industry Specifications Specification LinkLPC Reference Manual COM Method Contact Information Appendix a Technical SupportAppendix a