Toshiba TECRA, M10 manual System Bios IRT processing

2 Troubleshooting Procedures 2.4 System Board Troubleshooting

Table 2-5 Debug port error status (2/8)

System BIOS IRT processing

F100	CPU setup	CPU	IS1050 (CPU Socket)
	Initialization of ICH, MCH, and	ICH(PCI register,	IS1050 (CPU Socket)
	Super I/O	PIT controller)	IC1200 (MCH)
F101	setup of SD controller	MCH(PCI register )	IC1600 (ICH)
		card controller	IC2000 (SD Cont.)
	setup of PIT	BIOSROM	IC3000 (BIOS ROM)
		Super I/O	IC3400 (Super I/O)
	Memory initialization	MCH(PCI register)	IC1200 (MCH)
	Memory error	RAM(SPD, memory)	CN1400 (RAM Conn.)
F102		ICH(PCI register,	CN1410 (RAM Conn.)
	setup for using RAM area
		CMOS)	IC1600 (ICH)
	check memory error of RAM area
		CPU	IS1050 (CPU Socket)
	memory error	BIOSROM	IC3000 (BIOS ROM)
F103	CPU setup	CPU	IS1050 (CPU Socket)
	CMOS setup	ICH(CMOS)	IC1600 (ICH)
	CMOS error	BIOSROM	IC3000 (BIOS ROM)
	Resume branch	ICH(CMOS)	CN1400 (RAM Conn.)
			CN1410 (RAM Conn.)
	BIOS processing reading
F104		BIOSROM	IC1600 (ICH)
	ROM read error	RAM	IC3000 (BIOS ROM)
			IC3300 (TPM)
F105	check of BIOS processing	EC/KBC(EC), TPM,	IC3200 (EC/KBC)
		CPU	IC3200(EEPROM)
			IS1050 (CPU Socket)
	RAM setup	CPU	IS1050 (CPU Socket)
		ICH(CMOS,PIC
F106			CN1400 (RAM Conn.)
		controller, I/O, MEM
			CN1410 (RAM Conn.)
	Initialization of ICH (APIC)	I/O)
			IC1600 (ICH)
		RAM
	Initialization of ICH (PIT)
	PIT initialization error	CPU
	CPU check		IC1000 (CLKGEN)
		ICH(PIT controller,
	check of ROM data		IS1050 (CPU Socket)
		MEM I/O, CMOS,I/O)
	SMI setup		IC1600 (ICH)
F107		Clock generator,
	Part number data distinction
		EC/KBC(EC),	IC3000 (BIOS ROM)
	Panel distinction		IC3200 (EC/KBC)
		BIOSROM
			CN5000 (LCD Conn.)
	CMOS check
		Panel(EEPROM)
	Clock generator setup
	CPU initialization

2-24 [CONFIDENTIAL] TECRA M10 Maintenance Manual (960-685)