Texas Instruments
VLYNQ Port
manual
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Functional Block Diagram
Signal Descriptions
Serial Bus Error Interrupts
Remote Configuration Registers
Reset Considerations
Power Management
Features
Aoptdisable
Page 2
2
SPRUE36A
–September
2007
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Page 1
Page 3
Image 2
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Contents
Users Guide
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Contents
Appendix B
Appendix C
List of Figures
List of Tables
Related Documentation From Texas Instruments
About This Document
Notational Conventions
Trademarks
Purpose of the Peripheral
Features
Introduction
Functional Block Diagram
Industry Standards Compliance Statement
Peripheral Architecture
Clock Control
Pin Multiplexing
Signal Descriptions
Vlynq Port Pins
Protocol Description
Vlynq Functional Description
Vlynq Module Structure
Write Operations
TxSM
Read Operations
Auto-Negotiation
Serial Interface Width Configuration
Initialization
Serial Interface Width
Address Translation
Address Translation Example Single Mapped Region
Register DM644x Vlynq Module
DM644x Vlynq Module
Remote Vlynq Module
Flow Control
Example 1. Address Translation Example
Hardware Reset Considerations
Reset Considerations
Software Reset Considerations
Interrupt Support
Interrupt Generation Mechanism Block Diagram
Writes to Interrupt Pending/Set Register
Remote Interrupts
Serial Bus Error Interrupts
DMA Event Support
Power Management
Emulation Considerations
Vlynq Port Controller Registers
Vlynq Port Registers
Vlynq Register Address Space
Block Name Start Address End Address Size
Revmaj Revmin
Revision Register Revid
Revision Register Revid Field Descriptions
Bit Field Value Description
Control Register Ctrl
Control Register Ctrl Field Descriptions
Aoptdisable
Bit Field
Status Register Stat
Status Register Stat Field Descriptions
No error
Lerror
Nointpend
Interrupt Priority Vector Status/Clear Register Intpri
Interrupt Status/Clear Register Intstatclr
Instat
Interrupt Pointer Register Intptr Field Descriptions
Interrupt Pending/Set Register Intpendset
Interrupt Pointer Register Intptr
Intset
Txadrmap
Transmit Address Map Register XAM
Address Map Register XAM Field Descriptions
RXADRSIZE1
Receive Address Map Size 1 Register RAMS1
Receive Address Map Offset 1 Register RAMO1
RXADROFFSET1
RXADRSIZE2
Receive Address Map Size 2 Register RAMS2
Receive Address Map Offset 2 Register RAMO2
RXADROFFSET2
RXADRSIZE3
Receive Address Map Size 3 Register RAMS3
Receive Address Map Offset 3 Register RAMO3
RXADROFFSET3
RXADRSIZE4
Receive Address Map Size 4 Register RAMS4
Receive Address Map Offset 4 Register RAMO4
RXADROFFSET4
Chip Version Register Chipver Field Descriptions
Chip Version Register Chipver
Auto Negotiation Register Autngo
Auto Negotiation Register Autngo Field Descriptions
Remote Configuration Registers
Vlynq Port Remote Controller Registers
Supported Ordered Sets
Appendix a Vlynq Protocol Specifications
Special 8b/10b Code Groups
Table A-1. Special 8b/10b Code Groups
Figure A-1. Packet Format 10-bit Symbol Representation
Vlynq 2.0 Packet Format
Field Value Description
Vlynq 2.X Packets
Vlynq 2.X Packets
Appendix B Write/Read Performance
Write Performance
Burst Size Interface Running at 76.5 MHZ
Table B-1. Scaling Factors
Burst Size in 32-bit words Data Bytes
Bit Words Mbits/sec Mbytes/sec
Read Performance
Table B-3. Relative Performance with Various Latencies
Additions/Modifications/Deletions
Appendix C Revision History
Table C-1. Document Revision History
Rfid
Products Applications
DSP
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