Texas Instruments VLYNQ Port manual Appendix B Write/Read Performance, Write Performance

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Appendix B

Appendix B Write/Read Performance

The following sections discuss the write versus read performance and how the throughput (read or write) should be calculated for a given data width and serial clock frequency.

Note: The data and throughput calculations shown here are sample calculations for most ideal situations. In general, the data rates depend on a variety of other factors, such as efficiency of read/write burst transactions, ability of buffering up read/write data, and how best it can be serially shifted out without stalling additional read/write data burst, remote and local components , both external and internal (device operations, board considerations, etc.).

B.1 Write Performance

The max write rate describes the maximum available data rate of the serial interface for transmission, taking into consideration the 8b/10b encoding overheads. This is calculated as follows:

Max write rate = VLYNQ Serial Clock (MHZ) × No. of Pins × 8b/10b encoding overhead

The 8b/10b encoding overhead essentially accounts for 20% overhead, thus the actual data throughput after subtraction of the encoding overhead gives a factor of 0.8. For example, if the VLYNQ clock is running at 99 MHZ on a 4 pin per direction interface, the raw data is 99 × 4 or 396 Mbps. After the 8B10B encoding is removed, the maximum write rate is 396 × 0.8 = 316.8 Mbps.

The total throughput on the VLYNQ interface includes both transmit and receive directions. Therefore, for the above configuration, a remote device can also be writing to the local device at the same data rates, then the total throughput is the sum of transmit and receive rates, or 633.6 Mbps.

In addition to the 8b/10b encoding, the packet structure for read/write operations also results in additional overheads. The VLYNQ module can transfer single 32-bit words or a burst of up to sixteen 32-bit words.

The packet structure of the writes is shown below, here each character represents a byte.

Write32 - caaaaddddT

WriteBurst - claaaaddddddddddddT

Where

T - EndOfPacket

d - data, dddd represents additional 32-bit words in burst, up to 16 words.

a - address

c - command

l - length

The example above illustrates that single writes require 6 bytes of overhead, while burst writes require

8 bytes of overhead (due to the additional length of the field). From this, a scaling factor can be calculated (data bytes/total bytes), as show in Table B-1. The actual throughput is then calculated as the [scaling factor] × [max write rate].

Table B-2compares the throughput using a VLYNQ interface running at 76.5 MHZ and 99 MHZ.

SPRUE36A –September 2007

Write/Read Performance

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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureVlynq Port Pins Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Initialization Serial Interface Width ConfigurationAuto-Negotiation Serial Interface WidthAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramSerial Bus Error Interrupts DMA Event SupportRemote Interrupts Emulation Considerations Power ManagementVlynq Register Address Space Vlynq Port RegistersVlynq Port Controller Registers Block Name Start Address End Address SizeRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersSpecial 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBurst Size in 32-bit words Data Bytes Table B-1. Scaling FactorsBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secTable B-3. Relative Performance with Various Latencies Read PerformanceAppendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid
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