Texas Instruments VLYNQ Port Interrupt Priority Vector Status/Clear Register Intpri, Nointpend

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VLYNQ Port Registers

3.4Interrupt Priority Vector Status/Clear Register (INTPRI)

The interrupt priority vector status/clear register (INTPRI) displays the highest priority vector with a pending interrupt when read. When writing, only bits [4:0] are valid, and the value represents the vector of the interrupt to be cleared. The INTPRI is shown in Figure 12 and described in Table 10.

Figure 12. Interrupt Priority Vector Status/Clear Register (INTPRI)

31	30			16
NOINTPEND		Reserved
R-1h		R-0
15		5	4	0
	Reserved			INSTAT
	R-0			R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 10. Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions

Bit	Field	Value	Description
31	NOINTPEND		Interrupt pending status.
		0	Indicates there is a pending interrupt.
		1	Indicates that there are no pending interrupts from the interrupt status/clear register.
30-5	Reserved	0	Reserved. Always read as 0. Writes have no effect.
			When read, this field displays the vector that is mapped to the highest priority interrupt bit that is
4-0	INSTAT	0-1Fh	pending from the interrupt status/clear register, with bit 0 as the highest priority, and bit 31 as the
			lowest. Writing the vector value back to this field clears the interrupt.

3.5Interrupt Status/Clear Register (INTSTATCLR)

The interrupt status/clear register (INTSTATCLR) indicates the unmasked interrupt status. The INTSTATCLR is shown in Figure 13 and described in Table 11.

Figure 13. Interrupt Status/Clear Register (INTSTATCLR)

31

0

INTCLR

R/W-0

LEGEND: R/W = Read/Write; -n= value after reset

Table 11. Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions

Bit	Field	Value	Description
31-0	INTCLR	0-FFFF FFFFh	This field indicates the unmasked status of each interrupt. Writing a 1 to any set bit in this field
			clears the corresponding interrupt. If there is a bit set in this register and if the INTLOCAL bit in
			the control register (CTRL) is also set, the VLYNQ interrupt (VLQINT) is asserted.

SPRUE36A –September 2007	VLYNQ Port	31
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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Notational Conventions About This DocumentRelated Documentation From Texas Instruments Trademarks Introduction FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureProtocol Description Signal DescriptionsVlynq Port Pins Pin MultiplexingVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Serial Interface Width Serial Interface Width ConfigurationInitialization Auto-NegotiationAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlInterrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramDMA Event Support Serial Bus Error InterruptsRemote Interrupts Emulation Considerations Power ManagementBlock Name Start Address End Address Size Vlynq Port RegistersVlynq Register Address Space Vlynq Port Controller RegistersBit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj RevminControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInstat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr NointpendIntset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field DescriptionsAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersTable A-1. Special 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Supported Ordered SetsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBit Words Mbits/sec Mbytes/sec Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Burst Size Interface Running at 76.5 MHZTable B-3. Relative Performance with Various Latencies Read PerformanceTable C-1. Document Revision History Appendix C Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid