Texas Instruments VLYNQ Port Receive Address Map Size 4 Register RAMS4, RXADRSIZE4, RXADROFFSET4

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VLYNQ Port Registers

3.15 Receive Address Map Size 4 Register (RAMS4)

The receive address map size 4 register (RAMS4) is used to identify the intended destination of inbound serial packets. The RAMS4 is shown in Figure 23 and described in Table 21.

Figure 23. Receive Address Map Size 4 Register (RAMS4)

31	2	1	0
RXADRSIZE4		Reserved
R/W-0			R-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 21. Receive Address Map Size 4 Register (RAMS4) Field Descriptions

Bit	Field	Value	Description
31-2	RXADRSIZE4	0-3FFF FFFFh	The RXADRSIZE4 field is used to determine if receive packets are destined for the fourth of
			four mapped address regions. RXADRSIZE4 is compared with the address contained in the
			receive packet. If the receive packet address is less than the value in RXADRSIZE4, the
			packet address is added to the receive address map offset 4 register (RAMO4) to obtain the
			translated address.
1-0	Reserved	0	Reserved. Always read as 0. Writes have no effect.

3.16 Receive Address Map Offset 4 Register (RAMO4)

The receive address map offset 4 register (RAMO4) is used with the receive address map size 4 register (RAMS4) to translate receive packet addresses to local device configuration bus addresses. The RAMS4 is shown in Figure 24 and described in Table 22.

Figure 24. Receive Address Map Offset 4 Register (RAMO4)

31	2	1	0
RXADROFFSET4		Reserved
R/W-0			R-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 22. Receive Address Map Offset 4 Register (RAMO4) Field Descriptions

Bit	Field	Value	Description
31-2	RXADROFFSET4	0-3FFF FFFFh	The RXADROFFSET4 field is used with the receive address map size 4 register (RAMS4)
			to determine the translated address for serial data. If the receive packet address is less
			than the value in RAMS4, the packet address is added to the contents of this register to
			obtain the translated address.
1-0	Reserved	0	Reserved. Always read as 0. Writes have no effect.

SPRUE36A –September 2007	VLYNQ Port	37
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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Notational Conventions About This DocumentRelated Documentation From Texas Instruments Trademarks Introduction FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureVlynq Port Pins Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Initialization Serial Interface Width ConfigurationAuto-Negotiation Serial Interface WidthAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramDMA Event Support Serial Bus Error InterruptsRemote Interrupts Emulation Considerations Power ManagementVlynq Register Address Space Vlynq Port RegistersVlynq Port Controller Registers Block Name Start Address End Address SizeRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersSpecial 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBurst Size in 32-bit words Data Bytes Table B-1. Scaling FactorsBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secTable B-3. Relative Performance with Various Latencies Read PerformanceTable C-1. Document Revision History Appendix C Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid