Texas Instruments VLYNQ Port Appendix a Vlynq Protocol Specifications, Special 8b/10b Code Groups

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Appendix A

Appendix A VLYNQ Protocol Specifications

VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allow for in-band packet delineation and control. The following sections include general 8b/10b coding definitions and their implementation.

A.1 Special 8b/10b Code Groups

Table A-1. Special 8b/10b Code Groups

Code Group Name	Octet Value	Octet Bits	Current RD -	Current RD +
K28.0	1C	0001 1100	001111 0100	110000 1011
K28.1	3C	0011 1100	001111 1001	110000 0110
K28.2	5C	0101 1100	001111 0101	110000 1010
K28.3	7C	0111 1100	001111 0011	110000 1100
K28.4	9C	1001 1100	001111 0010	110000 1101
K28.5	BC	1011 1100	001111 1010	110000 0101
K28.6	DC	1101 1100	001111 0110	110000 1001
K28.7	FC	1111 1100	001111 1000	110000 0111
K23.7	F7	1111 0111	111010 1000	000101 0111
K27.7	FB	1111 1011	110110 1000	001001 0111
K29.7	FD	1111 1101	101110 1000	010001 0111
K30.7	FE	1111 1110	011110 1000	100001 0111

A.2 Supported Ordered Sets

Each VLYNQ module must support a limited number of ordered sets. Ordered sets provide for the delineation of packets and synchronization between VLYNQ modules at opposite ends of the serial connection. VLYNQ 2.0 and later versions do not require some of the following ordered sets.

Table A-2. Supported Ordered Sets

Code	Ordered Set	Encoding	Octet Value
/I/	Idle	/K28.5/	BC
/T/	End of Packet	/K29.7/	FD
/M/	Byte Disable	/K23.7/	F7
/P/	Flow Control Enable	/K28.0/	IC
/C/	Flow Control Disable	/K28.2/	5C
/E/	Error Indication	/K28.1/	3C
/0/	Init0	/K28.4/	9C
/I/	Init1	/K28.6/	DC
/L/	Link	/K30.7/	FE

40	VLYNQ Protocol Specifications	SPRUE36A –September 2007
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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Notational Conventions About This DocumentRelated Documentation From Texas Instruments Trademarks Introduction FeaturesPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementPeripheral Architecture Clock ControlSignal Descriptions Vlynq Port PinsPin Multiplexing Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations TxSMRead Operations Serial Interface Width Configuration InitializationAuto-Negotiation Serial Interface WidthAddress Translation Address Translation Example Single Mapped Region Register DM644x Vlynq ModuleDM644x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleReset Considerations Software Reset ConsiderationsHardware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterDMA Event Support Serial Bus Error InterruptsRemote Interrupts Power Management Emulation ConsiderationsVlynq Port Registers Vlynq Register Address SpaceVlynq Port Controller Registers Block Name Start Address End Address SizeRevision Register Revid Revision Register Revid Field DescriptionsRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorInterrupt Priority Vector Status/Clear Register Intpri Interrupt Status/Clear Register IntstatclrNointpend InstatInterrupt Pending/Set Register Intpendset Interrupt Pointer Register IntptrInterrupt Pointer Register Intptr Field Descriptions IntsetAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap Receive Address Map Size 1 Register RAMS1 Receive Address Map Offset 1 Register RAMO1RXADRSIZE1 RXADROFFSET1Receive Address Map Size 2 Register RAMS2 Receive Address Map Offset 2 Register RAMO2RXADRSIZE2 RXADROFFSET2Receive Address Map Size 3 Register RAMS3 Receive Address Map Offset 3 Register RAMO3RXADRSIZE3 RXADROFFSET3Receive Address Map Size 4 Register RAMS4 Receive Address Map Offset 4 Register RAMO4RXADRSIZE4 RXADROFFSET4Chip Version Register Chipver Auto Negotiation Register AutngoChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsRemote Configuration Registers Vlynq Port Remote Controller RegistersAppendix a Vlynq Protocol Specifications Special 8b/10b Code GroupsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Appendix B Write/Read Performance Write PerformanceTable B-1. Scaling Factors Burst Size in 32-bit words Data BytesBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesTable C-1. Document Revision History Appendix C Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid