Texas Instruments VLYNQ Port manual List of Figures

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	List of Figures
1	VLYNQ Port Functional Block Diagram	10
2	External Clock Block Diagram	11
3	Internal Clock Block Diagram	11
4	VLYNQ Module Structure	13
5	Write Operations	14
6	Read Operations	15
7	Example Address Memory Map	18
8	Interrupt Generation Mechanism Block Diagram	22
9	Revision Register (REVID)	26
10	Control Register (CTRL)	27
11	Status Register (STAT)	29
12	Interrupt Priority Vector Status/Clear Register (INTPRI)	31
13	Interrupt Status/Clear Register (INTSTATCLR)	31
14	Interrupt Pending/Set Register (INTPENDSET)	32
15	Interrupt Pointer Register (INTPTR)	32
16	Transmit Address Map Register (XAM)	33
17	Receive Address Map Size 1 Register (RAMS1)	34
18	Receive Address Map Offset 1 Register (RAMO1)	34
19	Receive Address Map Size 2 Register (RAMS2)	35
20	Receive Address Map Offset 2 Register (RAMO2)	35
21	Receive Address Map Size 3 Register (RAMS3)	36
22	Receive Address Map Offset 3 Register (RAMO3)	36
23	Receive Address Map Size 4 Register (RAMS4)	37
24	Receive Address Map Offset 4 Register (RAMO4)	37
25	Chip Version Register (CHIPVER)	38
26	Auto Negotiation Register (AUTNGO)	38
A-1	Packet Format (10-bit Symbol Representation)	41

SPRUE36A –September 2007

List of Figures

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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Related Documentation From Texas Instruments About This DocumentNotational Conventions Trademarks Purpose of the Peripheral FeaturesIntroduction Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureVlynq Port Pins Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Initialization Serial Interface Width ConfigurationAuto-Negotiation Serial Interface WidthAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramRemote Interrupts Serial Bus Error InterruptsDMA Event Support Emulation Considerations Power ManagementVlynq Register Address Space Vlynq Port RegistersVlynq Port Controller Registers Block Name Start Address End Address SizeRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersSpecial 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBurst Size in 32-bit words Data Bytes Table B-1. Scaling FactorsBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secTable B-3. Relative Performance with Various Latencies Read PerformanceAdditions/Modifications/Deletions Appendix C Revision HistoryTable C-1. Document Revision History Rfid Products ApplicationsDSP