Texas Instruments VLYNQ Port manual Status Register Stat Field Descriptions

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VLYNQ Port Registers

3.3Status Register (STAT)

The status register (STAT) is used to detect conditions that may be of interest to the system designer. The STAT is shown in Figure 11 and described in Table 9.

Figure 11. Status Register (STAT)

31	28	27	24	23	20	19	15
Reserved		SWIDTHIN		SWIDTHOUT		Reserved
	R-0		R-0		R-0		R-0
14			12	11	10	9	8
	RXCURRENTSAMPLE			RTM	IFLOW	OFLOW	RERROR
		R-0		R-1	R-0	R-0	W1C-0
7	6	5	4	3	2	1	0
LERROR	NFEMPTY3	NFEMPTY2	NFEMPTY1	NFEMPTY0	SPEND	MPEND	LINK
W1C-0	R-0	R-0	R-0	R-0	R-0	R-0	R-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear bit; -n= value after reset; x= reset value is indeterminate

Table 9. Status Register (STAT) Field Descriptions

Bit	Field	Value	Description
31-28	Reserved	0	Reserved. Always read as 0. Writes have no effect.
27-24	SWIDTHIN	0-Fh	Size of the inbound serial data. Indicates the number of receive pins that are being used to
		0-Fh	establish the serial interface.
			establish the serial interface.
		0	No pins used
		1h	1	RX pin used
		2h	2	RX pins used
		3h	3	RX pins used
		4h	4	RX pins used
		5h-Fh	Reserved
23-20	SWIDTHOUT	0-Fh	Size of the outbound serial data. Indicates the number of transmit pins that are being used
			to establish the serial interface.
		0	No pins used
		1h	1	TX pin used
		2h	2	TX pins used
		3h	3	TX pins used
		4h	4	TX pins used
		5h-Fh	Reserved
19-15	Reserved	0	Reserved. Always read as 0. Writes have no effect.
14-12	RXCURRENTSAMPLE	0-Fh	Current RTM sample. Indicates the current clock sample value used by RTM.
11	RTM	1	RTM enable. Always read as 1. Indicates that the VLYNQ module on the DM644x DMSoC
			has the receive timing manager (RTM).

10 IFLOW

0

1

9 OFLOW

0

1

Inbound flow control.

Free to transmit.

Indicates that a flow control enable request has been received and has stalled transmit until a flow control disable request is received.

Outbound flow control. Indicates the status of the two inbound FIFOs (FIFO1 or FIFO2). Indicates that the internal flow control threshold is not yet reached.

Indicates that the internal flow control threshold has been reached (FIFO1 or FIFO2 is full) and a flow control enable request has been sent to the remote device.

SPRUE36A –September 2007	VLYNQ Port	29
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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Related Documentation From Texas Instruments About This DocumentNotational Conventions Trademarks Purpose of the Peripheral FeaturesIntroduction Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureVlynq Port Pins Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Initialization Serial Interface Width ConfigurationAuto-Negotiation Serial Interface WidthAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramRemote Interrupts Serial Bus Error InterruptsDMA Event Support Emulation Considerations Power ManagementVlynq Register Address Space Vlynq Port RegistersVlynq Port Controller Registers Block Name Start Address End Address SizeRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersSpecial 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBurst Size in 32-bit words Data Bytes Table B-1. Scaling FactorsBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secTable B-3. Relative Performance with Various Latencies Read PerformanceAdditions/Modifications/Deletions Appendix C Revision HistoryTable C-1. Document Revision History Rfid Products ApplicationsDSP