Texas Instruments VLYNQ Port manual Reset Considerations, Interrupt Support

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Peripheral Architecture

2.11 Reset Considerations

2.11.1Software Reset Considerations

Peripheral clock and reset control is done through the power and sleep controller (PSC) module that is included with the device. For more information, refer to the power management section (Section 2.14). Additionally, there is a software reset (the reset bit in the VLYNQ control register, CTRL) within the peripheral itself. Writing a 1 to the reset bit resets all of the internal state machines of the VLYNQ module, the serial interface is disabled, and the link is lost. The VLYNQ module remains in reset until the software clears the bit.

Note: When setting the reset bit, the VLYNQ status register (STAT) value is the only value that is set to the default value. All of the other VLYNQ memory-mapped registers retain their values prior to the software reset.

2.11.2Hardware Reset Considerations

When a hardware reset occurs, the VLYNQ peripheral resets its register values to the default values and the serial interface is disabled. After a hardware reset, the VLYNQ memory mapped registers and any chip-level registers that are associated with VLYNQ (for example, pin multiplexing registers) must be configured appropriately before data transmission can resume.

CAUTION

Be cautious when only resetting one of the VLYNQ devices after two or more VLYNQ devices have established a link. If only one of the VLYNQ devices is in reset, then no data activity can occur across the serial interface during the time of reset.

2.12 Interrupt Support

2.12.1Interrupt Events and Requests

The VLYNQ module interrupt VLQINT is mapped to the ARM interrupt controller (ARM INT31). For more information on the ARM interrupt controller (AINTC), see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (SPRUE14).

Interrupts generate when bits are set in the VLYNQ interrupt pending/set register (INTPENDSET). Bits are set in the INTPENDSET register when any of the following occur:

∙Writing directly to the INTPENDSET

∙Remote interrupt (via the serial interrupt packet)

∙Serial bus error

When the VLYNQ interrupt pending/set register (INTPENDSET) is a non-zero value, the method of forwarding the interrupt status depends on the state of the INTLOCAL bit in the VLYNQ control register (CTRL).

When INTLOCAL = 0, the contents of INTPENDSET are inserted into an interrupt packet and sent over the serial interface. When packet transmission completes, the associated bits clear in INTPENDSET. When INTLOCAL = 1, bits in INTPENDSET transfer to the VLYNQ interrupt status/clear register (INTSTATCLR). The logical-OR of all of the bits in INTSTATCLR is driven onto the interrupt line, causing the VLYNQINT to pulse.

If the system writes to INTSTATCLR while interrupts are still pending, a new VLQINT interrupt is generated.

The VLYNQ interrupt generation mechanism is shown in Figure 8.

SPRUE36A –September 2007

VLYNQ Port

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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureVlynq Port Pins Signal DescriptionsPin Multiplexing Protocol DescriptionVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Initialization Serial Interface Width ConfigurationAuto-Negotiation Serial Interface WidthAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlSoftware Reset Considerations Reset ConsiderationsHardware Reset Considerations Interrupt SupportWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramSerial Bus Error Interrupts DMA Event SupportRemote Interrupts Emulation Considerations Power ManagementVlynq Register Address Space Vlynq Port RegistersVlynq Port Controller Registers Block Name Start Address End Address SizeRevision Register Revid Field Descriptions Revision Register RevidRevmaj Revmin Bit Field Value DescriptionControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInterrupt Status/Clear Register Intstatclr Interrupt Priority Vector Status/Clear Register IntpriNointpend InstatInterrupt Pointer Register Intptr Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Field Descriptions IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap Receive Address Map Offset 1 Register RAMO1 Receive Address Map Size 1 Register RAMS1RXADRSIZE1 RXADROFFSET1Receive Address Map Offset 2 Register RAMO2 Receive Address Map Size 2 Register RAMS2RXADRSIZE2 RXADROFFSET2Receive Address Map Offset 3 Register RAMO3 Receive Address Map Size 3 Register RAMS3RXADRSIZE3 RXADROFFSET3Receive Address Map Offset 4 Register RAMO4 Receive Address Map Size 4 Register RAMS4RXADRSIZE4 RXADROFFSET4Auto Negotiation Register Autngo Chip Version Register ChipverChip Version Register Chipver Field Descriptions Auto Negotiation Register Autngo Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersSpecial 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSupported Ordered Sets Table A-1. Special 8b/10b Code GroupsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBurst Size in 32-bit words Data Bytes Table B-1. Scaling FactorsBurst Size Interface Running at 76.5 MHZ Bit Words Mbits/sec Mbytes/secTable B-3. Relative Performance with Various Latencies Read PerformanceAppendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid
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