Texas Instruments VLYNQ Port manual No error, Lerror

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VLYNQ Port Registers

Table 9. Status Register (STAT) Field Descriptions (continued)

Bit	Field	Value	Description
8	RERROR		Remote Error. Write a 1 to this bit to clear it.
		0	No error
		1	This bit indicates that a downstream VLYNQ module has detected a packet error. This bit is
		1	set when an error indication, /E/, is received from the serial interface. See Appendix A.

			If this bit is set, and the INTENABLE (bit 13 in VLYNQ control register) is also set, it asserts
			the VLYNQ interrupt (VLQINT).
7	LERROR		Local error. Write a 1 to this bit to clear it.
		0	No error.
		1	This bit indicates that an inbound packet contains an error that is detected by the local
		1	VLYNQ module.
			VLYNQ module.
			If this bit is set, and the INTENABLE (bit 13 in VLYNQ control register) is also set, it asserts
			the VLYNQ interrupt (VLQINT).
6	NFEMPTY3		FIFO 3 is not empty.
		0	Indicates that the slave command FIFO is empty.
		1	Indicates that the slave command FIFO is not empty.
5	NFEMPTY2		FIFO 2 is not empty.
		0	Indicates that the slave data FIFO is empty.
		1	Indicates that the slave data FIFO is not empty.
4	NFEMPTY1		FIFO 1 is not empty.
		0	Indicates that the master command FIFO is empty.
		1	Indicates that the master command FIFO is not empty.
3	NFEMPTY0		FIFO 0 is not empty.
		0	Indicates that the master data FIFO is empty.
		1	Indicates that the master data FIFO is not empty.
2	SPEND		Pending slave request.
		0	No pending slave requests.
		1	Indicates detection of a transfer request initiated by the VLYNQ module to the off-chip
		1	peripheral (TX slave configuration bus interface).
			peripheral (TX slave configuration bus interface).
1	MPEND		Pending master requests.
		0	No pending master requests.
		1	Indicates detection of a transfer request initiated by an off-chip peripheral to the VLYNQ
		1	module (RX master configuration bus interface).
			module (RX master configuration bus interface).
0	LINK		Link
		0	Indicates that the serial interface initialization sequence has not yet completed or the link
			has timed out.
		1	Indicates that the serial interface initialization sequence has completed successfully.

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VLYNQ Port

SPRUE36A –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementPeripheral Architecture Clock ControlPin Multiplexing Signal DescriptionsVlynq Port Pins Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations TxSMRead Operations Auto-Negotiation Serial Interface Width ConfigurationInitialization Serial Interface WidthAddress Translation Address Translation Example Single Mapped Region Register DM644x Vlynq ModuleDM644x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterSerial Bus Error Interrupts DMA Event SupportRemote Interrupts Power Management Emulation ConsiderationsVlynq Port Controller Registers Vlynq Port RegistersVlynq Register Address Space Block Name Start Address End Address SizeRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsRemote Configuration Registers Vlynq Port Remote Controller RegistersSupported Ordered Sets Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Appendix B Write/Read Performance Write PerformanceBurst Size Interface Running at 76.5 MHZ Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesAppendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid