Texas Instruments VLYNQ Port manual Read Operations

Page 15

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Peripheral Architecture

2.5.2Read Operations

Read requests from the slave configuration bus interface are written to the outbound CMD FIFO (similar to the write requests). Data is subsequently read from the FIFO and encapsulated into a read request packet. The packet is encoded and serialized before it is transmitted to the remote device. Next, the remote device deserializes, decodes the receive data, and writes the receive data to the inbound CMD FIFO. After reading the address from the FIFO, a master configuration bus interface read operation initiates in the remote device. When the remote master configuration bus interface receives the read data, the data is written to the return data FIFO before it is encoded and serialized. When the receive data reaches the local VLYNQ module, it is deserialized, decoded, and written to the return data FIFO (local device). Finally, the read data is transferred on the local device’s slave configuration interface.

The data flow between two connected VLYNQ devices with read requests that originate from the DM644x device is shown in Figure 6. The remote VLYNQ device returns the read data. Read data is shown with dotted arrows.

Figure 6. Read Operations

 

 

System￿clock

 

VLYNQ￿Clock

 

 

 

 

 

 

 

 

 

Serial

 

Slave

Address

Outbound

Outbound

 

8B/10B

TxData

 

config￿bus

command

TxSM

Serializer

 

translation

commands

encoding

 

interface

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

Return

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

Registers

 

 

 

Local￿VLYNC

 

 

 

 

 

 

 

 

 

 

 

 

Return

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

Serial

 

Master

Address

Inbound

Inbound

 

8B/10B

RxData

 

config￿bus

command

RxSM

Deserializer

 

translation

commands

decoding

 

interface

FIFO

 

 

 

 

 

 

 

 

 

 

 

System￿clock

 

VLYNQ￿Clock

 

 

 

 

 

 

 

 

 

Serial

 

Slave

Address

Outbound

Outbound

 

8B/10B

TxData

 

config￿bus

command

TxSM

Serializer

 

translation

commands

encoding

 

interface

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Return

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

Registers

 

 

 

Remote￿VLYNQ

 

 

 

 

 

 

 

 

 

 

 

 

Return

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

FIFO

 

 

 

 

 

 

 

 

 

 

Serial

 

Master

Address

Inbound

Inbound

 

8B/10B

RxData

 

config￿bus

command

RxSM

Deserializer

 

translation

commands

decoding

 

interface

FIFO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPRUE36A –September 2007

 

 

 

 

VLYNQ Port

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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureProtocol Description Signal DescriptionsVlynq Port Pins Pin MultiplexingVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Serial Interface Width Serial Interface Width ConfigurationInitialization Auto-NegotiationAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlInterrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramSerial Bus Error Interrupts DMA Event SupportRemote Interrupts Emulation Considerations Power ManagementBlock Name Start Address End Address Size Vlynq Port RegistersVlynq Register Address Space Vlynq Port Controller RegistersBit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj RevminControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInstat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr NointpendIntset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field DescriptionsTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersTable A-1. Special 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Supported Ordered SetsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBit Words Mbits/sec Mbytes/sec Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Burst Size Interface Running at 76.5 MHZTable B-3. Relative Performance with Various Latencies Read PerformanceAppendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid