Texas Instruments VLYNQ Port Receive Address Map Size 2 Register RAMS2, RXADRSIZE2, RXADROFFSET2

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VLYNQ Port Registers

3.11 Receive Address Map Size 2 Register (RAMS2)

The receive address map size 2 register (RAMS2) is used to identify the intended destination of inbound serial packets. The RAMS2 is shown in Figure 19 and described in Table 17.

Figure 19. Receive Address Map Size 2 Register (RAMS2)

31	2	1	0
RXADRSIZE2		Reserved
R/W-0			R-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 17. Receive Address Map Size 2 Register (RAMS2) Field Descriptions

Bit	Field	Value	Description
31-2	RXADRSIZE2	0-3FFF FFFFh	The RXADRSIZE2 field is used to determine if receive packets are destined for the second
			of four mapped address regions. RXADRSIZE2 is compared with the address contained in
			the receive packet. If the received packet address is less than the value in RXADRSIZE2,
			the packet address is added to the receive address map offset 2 register (RAMO2) to obtain
			the translated address.
1-0	Reserved	0	Reserved. Always read as 0. Writes have no effect.

3.12 Receive Address Map Offset 2 Register (RAMO2)

The receive address map offset 2 register (RAMO2) is used with the receive address map size 2 register (RAMS2) to translate receive packet addresses to local device configuration bus addresses. The RAMO2 is shown in Figure 20 and described in Table 18.

Figure 20. Receive Address Map Offset 2 Register (RAMO2)

31	2	1	0
RXADROFFSET2		Reserved
R/W-0			R-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 18. Receive Address Map Offset 2 Register (RAMO2) Field Descriptions

Bit	Field	Value	Description
31-2	RXADROFFSET2	0-3FFF FFFFh	The RXADROFFSET2 field is used with the receive address map size 2 register (RAMS2)
			to determine the translated address for serial data. If the received packet address is less
			than the value in RAMS2, the packet address is added to the contents of this register to
			obtain the translated address.
1-0	Reserved	0	Reserved. Always read as 0. Writes have no affect.

SPRUE36A –September 2007	VLYNQ Port	35
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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Related Documentation From Texas Instruments About This DocumentNotational Conventions Trademarks Purpose of the Peripheral FeaturesIntroduction Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureProtocol Description Signal DescriptionsVlynq Port Pins Pin MultiplexingVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Serial Interface Width Serial Interface Width ConfigurationInitialization Auto-NegotiationAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlInterrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramRemote Interrupts Serial Bus Error InterruptsDMA Event Support Emulation Considerations Power ManagementBlock Name Start Address End Address Size Vlynq Port RegistersVlynq Register Address Space Vlynq Port Controller RegistersBit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj RevminControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInstat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr NointpendIntset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field DescriptionsTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersTable A-1. Special 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Supported Ordered SetsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBit Words Mbits/sec Mbytes/sec Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Burst Size Interface Running at 76.5 MHZTable B-3. Relative Performance with Various Latencies Read PerformanceAdditions/Modifications/Deletions Appendix C Revision HistoryTable C-1. Document Revision History Rfid Products ApplicationsDSP