Texas Instruments VLYNQ Port Receive Address Map Size 1 Register RAMS1, RXADRSIZE1, RXADROFFSET1

Page 34

www.ti.com

VLYNQ Port Registers

3.9Receive Address Map Size 1 Register (RAMS1)

The receive address map size 1 register (RAMS1) is used to identify the intended destination of inbound serial packets. The RAMS1 is shown in Figure 17 and described in Table 15.

Figure 17. Receive Address Map Size 1 Register (RAMS1)

31

2

1

0

RXADRSIZE1

 

Reserved

R/W-0

 

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

 

Table 15. Receive Address Map Size 1 Register (RAMS1) Field Descriptions

Bit

Field

Value

Description

31-2

RXADRSIZE1

0-3FFF FFFFh

The RXADRSIZE1 field is used to determine if receive packets are destined for the first of

 

 

 

four mapped address regions. RXADRSIZE1 is compared with the address contained in the

 

 

 

receive packet. If the received packet address is less than the value in RXADRSIZE1, the

 

 

 

packet address is added to the receive address map offset 1 register (RAMO1) to obtain the

 

 

 

translated address.

1-0

Reserved

0

Reserved. Always read as 0. Writes have no effect.

3.10 Receive Address Map Offset 1 Register (RAMO1)

The receive address map offset 1 register (RAMO1) is used with the receive address map size 1 register (RAMS1) to translate receive packet addresses to local device configuration bus addresses. The RAMO1 is shown in Figure 18 and described in Table 16.

Figure 18. Receive Address Map Offset 1 Register (RAMO1)

31

2

1

0

RXADROFFSET1

 

Reserved

R/W-0

 

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

 

Table 16. Receive Address Map Offset 1 Register (RAMO1) Field Descriptions

Bit

Field

Value

Description

31-2

RXADROFFSET1

0-3FFF FFFFh

The RXADROFFSET1 field is used with the receive address map size 1 register (RAMS1)

 

 

 

to determine the translated address for serial data. If the received packet address is less

 

 

 

than the value in RAMS1, the packet address is added to the contents of this register to

 

 

 

obtain the translated address.

1-0

Reserved

0

Reserved. Always read as 0. Writes have no effect.

34

VLYNQ Port

SPRUE36A –September 2007

Page 33 Page 35
Image 34
Page 33 Page 35
Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Notational Conventions About This DocumentRelated Documentation From Texas Instruments Trademarks Introduction FeaturesPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementPeripheral Architecture Clock ControlPin Multiplexing Signal DescriptionsVlynq Port Pins Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations TxSMRead Operations Auto-Negotiation Serial Interface Width ConfigurationInitialization Serial Interface WidthAddress Translation Address Translation Example Single Mapped Region Register DM644x Vlynq ModuleDM644x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterDMA Event Support Serial Bus Error InterruptsRemote Interrupts Power Management Emulation ConsiderationsVlynq Port Controller Registers Vlynq Port RegistersVlynq Register Address Space Block Name Start Address End Address SizeRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetAddress Map Register XAM Field Descriptions Transmit Address Map Register XAMTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsRemote Configuration Registers Vlynq Port Remote Controller RegistersSupported Ordered Sets Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Appendix B Write/Read Performance Write PerformanceBurst Size Interface Running at 76.5 MHZ Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesTable C-1. Document Revision History Appendix C Revision HistoryAdditions/Modifications/Deletions DSP Products ApplicationsRfid
Top Page Image Contents