Texas Instruments VLYNQ Port manual Contents

Contents

Preface				7
1	Introduction			9
	1.1	Purpose of the Peripheral		9
	1.2	Features		9
	1.3	Functional Block Diagram		10
	1.4	Industry Standard(s) Compliance Statement		10
2	Peripheral Architecture			11
	2.1	Clock Control		11
	2.2	Signal Descriptions		12
	2.3	Pin Multiplexing		12
	2.4	Protocol Description		12
	2.5	VLYNQ Functional Description		13
	2.6	Initialization		16
	2.7	Auto-Negotiation		16
	2.8	Serial Interface Width Configuration		16
	2.9	Address Translation		17
	2.10	Flow Control		20
	2.11	Reset Considerations		21
	2.12	Interrupt Support		21
	2.13	DMA Event Support		23
	2.14	Power Management		24
	2.15	Emulation Considerations		24
3	VLYNQ Port Registers			25
	3.1	Revision Register (REVID)		26
	3.2	Control Register (CTRL)		27
	3.3	Status Register (STAT)		29
	3.4	Interrupt Priority Vector Status/Clear Register (INTPRI)		31
	3.5	Interrupt Status/Clear Register (INTSTATCLR)		31
	3.6	Interrupt Pending/Set Register (INTPENDSET)		32
	3.7	Interrupt Pointer Register (INTPTR)		32
	3.8	Transmit Address Map Register (XAM)		33
	3.9	Receive Address Map Size 1 Register (RAMS1)		34
	3.10	Receive Address Map Offset 1 Register (RAMO1)		34
	3.11	Receive Address Map Size 2 Register (RAMS2)		35
	3.12	Receive Address Map Offset 2 Register (RAMO2)		35
	3.13	Receive Address Map Size 3 Register (RAMS3)		36
	3.14	Receive Address Map Offset 3 Register (RAMO3)		36
	3.15	Receive Address Map Size 4 Register (RAMS4)		37
	3.16	Receive Address Map Offset 4 Register (RAMO4)		37
	3.17	Chip Version Register (CHIPVER)		38
	3.18	Auto Negotiation Register (AUTNGO)		38
4	Remote Configuration Registers			39
Appendix A		VLYNQ Protocol Specifications		40
	A.1	Special 8b/10b Code Groups		40
SPRUE36A –September 2007			Table of Contents	3

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