Texas Instruments VLYNQ Port manual Read Performance

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Read Performance

B.2 Read Performance

Since reads must complete a transmit-remote read-receive cycle before starting another read transaction, the data throughput is lower as compared to writes. There is latency involved in reading the data from the remote device; and in some cases, a local latency in writing the returned data before the next read can start.

The max read rate is calculated the same way as the max write rate. The packet overhead is as shown below:

Read32 - caaaaT

ReadBurst - claaaaT

ReadReturn - clddddddddT

Where

T - EndOfPacket

d - data, dddd represents additional 32-bit words in burst, up to 16 words.

a - address

c - command

l - length

There are 6 bytes of overhead for a single read, 7 bytes for burst reads, and 3 bytes for read returns. The time required for a read is the total of the time for the read request, remote latency, read return, and local latency. Thus, the throughput can be calculated as data bytes/total transaction time, where the latency of both local and remote devices is combined.

Read Throughput = data/ (((Read + ReadReturn + data)/max read rate) + Latency

=(data × max read rate)/((Read + ReadReturn + data) + Latency × max read rate)

For example, with a 4 pin, 99 MHZ VLYNQ connection, for a single 32-bit word read:

Read Throughput = 32 bits × 316.8 Mbps/ (6 × 8 + 3 × 8 + 4 × 8 + Latency × 316.8Mbps)

= 10137.6/(104 + Latency × 316.8 Mbps)

Similarly, for a burst read of sixteen 32-bit words, with a 4 pin, 99 MHZ VLYNQ connection

Read Throughput = 16 × 32 bits × 316.8Mbps/(6 × 8 + 3 × 8 + 16 × 4 × 8 + Latency × 316.8Mbps) = 162201.6/(584 + Latency × 316.8Mbps)

Using the formula above, the relative performance with various latencies is illustrated for a 4 pin, 99 MHZ VLYNQ clock, burst read (sixteen 32-bit words) throughput rate, as shown in Table B-3:

Table B-3. Relative Performance with Various Latencies

Number of VLYNQ Pins

 

Latency (μsec)

Throughput

Throughput

(99 MHZ)

Burst Size in 32-bit Words

(Mbits/sec)

(Mbytes/sec)

4

16

0

277.74

34.72

 

 

1

179.70

22.46

 

 

10

43.02

5.38

 

 

100

5.00

0.62

To efficiently use VLYNQ bandwidth, it is desirable for each VLYNQ device to write from the local device to the remote device. Burst transactions are more efficient than single read/write transactions.

SPRUE36A –September 2007

Write/Read Performance

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Contents Users Guide Submit Documentation Feedback Contents Appendix C Appendix BList of Figures List of Tables Related Documentation From Texas Instruments About This DocumentNotational Conventions Trademarks Purpose of the Peripheral FeaturesIntroduction Industry Standards Compliance Statement Functional Block DiagramClock Control Peripheral ArchitectureProtocol Description Signal DescriptionsVlynq Port Pins Pin MultiplexingVlynq Module Structure Vlynq Functional DescriptionTxSM Write OperationsRead Operations Serial Interface Width Serial Interface Width ConfigurationInitialization Auto-NegotiationAddress Translation Register DM644x Vlynq Module Address Translation Example Single Mapped RegionRemote Vlynq Module DM644x Vlynq ModuleExample 1. Address Translation Example Flow ControlInterrupt Support Reset ConsiderationsSoftware Reset Considerations Hardware Reset ConsiderationsWrites to Interrupt Pending/Set Register Interrupt Generation Mechanism Block DiagramRemote Interrupts Serial Bus Error InterruptsDMA Event Support Emulation Considerations Power ManagementBlock Name Start Address End Address Size Vlynq Port RegistersVlynq Register Address Space Vlynq Port Controller RegistersBit Field Value Description Revision Register RevidRevision Register Revid Field Descriptions Revmaj RevminControl Register Ctrl Field Descriptions Control Register CtrlBit Field AoptdisableStatus Register Stat Field Descriptions Status Register StatLerror No errorInstat Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr NointpendIntset Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr Interrupt Pointer Register Intptr Field DescriptionsTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions RXADROFFSET1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADRSIZE1RXADROFFSET2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADRSIZE2RXADROFFSET3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADRSIZE3RXADROFFSET4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADRSIZE4Auto Negotiation Register Autngo Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Chip Version Register Chipver Field DescriptionsVlynq Port Remote Controller Registers Remote Configuration RegistersTable A-1. Special 8b/10b Code Groups Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Supported Ordered SetsVlynq 2.0 Packet Format Figure A-1. Packet Format 10-bit Symbol RepresentationField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Write Performance Appendix B Write/Read PerformanceBit Words Mbits/sec Mbytes/sec Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Burst Size Interface Running at 76.5 MHZTable B-3. Relative Performance with Various Latencies Read PerformanceAdditions/Modifications/Deletions Appendix C Revision HistoryTable C-1. Document Revision History Rfid Products ApplicationsDSP
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