Texas Instruments VLYNQ Port manual Field Value Description

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VLYNQ 2.0 Packet Format

Table A-3. Packet Format (10-bit Symbol Representation) Description

Field

Value

Description

PKTTYPE[3:0]

 

This field indicates the packet type.

 

0000

Reserved

 

0001

Write with address increment.

 

0010

Reserved

 

0011

Write 32-bit word with address increment.

 

0100

Reserved

 

0101

Configuration write with address increment.

 

0110

Reserved for extended command indicator (cmd2).

 

0111

Interrupt

 

1000

Reserved

 

1001

Read with address increment.

 

1010

Reserved

 

1011

Read 32-bit word with address increment.

 

1100

Reserved

 

1101

Configuration read with address increment.

 

1110

Reserved for VLYNQ version 2.0 and later.

 

1111

Read response for all VLYNQ versions.

ADRMASK[3:0]

 

Indicates which byte of the address is included in the packet. Only address bytes that have changed

 

 

since the previous address will be included. Each bit corresponds to one byte of address.

BYTECNT[7:0]

 

Byte count. This field indicates the total number of bytes in the packet. This field is only included for

 

 

write, read, and configuration packet types. All other packet types have fixed lengths and do not

 

 

require this field.

ADDRESS[7:0]

 

Address byte 0. This byte is included only if ADRMASK[0] is set to 1. If ADRMASK[0] is cleared to 0,

 

 

assume this byte is equal to bits 7:0 of the previous address. Read response packets do not include

 

 

this field.

ADDRESS[15:8]

 

Address byte 1. This byte is included only if ADRMASK[1] is set to 1. If ADRMASK[1] is cleared to 0,

 

 

assume this byte is equal to bits 15:8 of the previous address. Read response packets do not include

 

 

this field.

ADDRESS[23:16]

 

Address byte 2. This byte is only included if ADRMASK[2] is set to 1. If ADRMASK[2] is cleared to 0,

 

 

this assume this byte is equal to bits 23:16 of the previous address. Read response packets do not

 

 

include this field.

ADDRESS[31:24]

 

Address byte 3. This byte is only included if ADRMASK[3] is set to 1. If ADRMASK[3] is cleared to 0,

 

 

assume this byte is equal to bits 31:24 of the previous address. Read response packets do not

 

 

include this field.

DATA

 

Data payload. The maximum data payload size is limited to sixteen 32-bit words to allow it to fit in the

 

 

RX FIFO.

EOP

 

End of packet indicator, /T/.

The CMD2 bit is only included in the packet, if the packet type indicates extended command (PKTTYPE = 0110).

Use configuration packet types to remotely access VLYNQ module registers. The configuration packet types do not depend on control register bit settings.

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VLYNQ Protocol Specifications

SPRUE36A –September 2007

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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables About This Document Notational ConventionsRelated Documentation From Texas Instruments Trademarks Features IntroductionPurpose of the Peripheral Functional Block Diagram Industry Standards Compliance StatementPeripheral Architecture Clock ControlPin Multiplexing Signal DescriptionsVlynq Port Pins Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations TxSMRead Operations Auto-Negotiation Serial Interface Width ConfigurationInitialization Serial Interface WidthAddress Translation Address Translation Example Single Mapped Region Register DM644x Vlynq ModuleDM644x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterSerial Bus Error Interrupts DMA Event SupportRemote Interrupts Power Management Emulation ConsiderationsVlynq Port Controller Registers Vlynq Port RegistersVlynq Register Address Space Block Name Start Address End Address SizeRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetTransmit Address Map Register XAM Address Map Register XAM Field DescriptionsTxadrmap RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsRemote Configuration Registers Vlynq Port Remote Controller RegistersSupported Ordered Sets Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Appendix B Write/Read Performance Write PerformanceBurst Size Interface Running at 76.5 MHZ Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesAppendix C Revision History Table C-1. Document Revision HistoryAdditions/Modifications/Deletions Products Applications DSPRfid
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