Texas Instruments VLYNQ Port manual Revision Register Revid Field Descriptions, Revmaj Revmin

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VLYNQ Port Registers

3.1Revision Register (REVID)

The revision register (REVID) contains the major and minor revisions for the VLYNQ module. The REVID is shown in Figure 9 and described in Table 7.

Figure 9. Revision Register (REVID)

31			16
		ID
		R-1h
15	8	7	0
	REVMAJ		REVMIN
	R-2h		R-6h

LEGEND: R = Read only; -n= value after reset

			Table 7. Revision Register (REVID) Field Descriptions
Bit	Field	Value	Description
31-16	ID	01h	Unique module ID.
15-8	REVMAJ	0-FFh	Major revision.
		2h	Current major revision.
7-0	REVMIN	0-FFh	Minor revision.
		6h	Current minor revision.

26	VLYNQ Port	SPRUE36A –September 2007
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Contents Users Guide Submit Documentation Feedback Contents Appendix B Appendix CList of Figures List of Tables Related Documentation From Texas Instruments About This DocumentNotational Conventions Trademarks Purpose of the Peripheral FeaturesIntroduction Functional Block Diagram Industry Standards Compliance StatementPeripheral Architecture Clock ControlPin Multiplexing Signal DescriptionsVlynq Port Pins Protocol DescriptionVlynq Functional Description Vlynq Module StructureWrite Operations TxSMRead Operations Auto-Negotiation Serial Interface Width ConfigurationInitialization Serial Interface WidthAddress Translation Address Translation Example Single Mapped Region Register DM644x Vlynq ModuleDM644x Vlynq Module Remote Vlynq ModuleFlow Control Example 1. Address Translation ExampleHardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Interrupt SupportInterrupt Generation Mechanism Block Diagram Writes to Interrupt Pending/Set RegisterRemote Interrupts Serial Bus Error InterruptsDMA Event Support Power Management Emulation ConsiderationsVlynq Port Controller Registers Vlynq Port RegistersVlynq Register Address Space Block Name Start Address End Address SizeRevmaj Revmin Revision Register RevidRevision Register Revid Field Descriptions Bit Field Value DescriptionControl Register Ctrl Control Register Ctrl Field DescriptionsAoptdisable Bit FieldStatus Register Stat Status Register Stat Field DescriptionsNo error LerrorNointpend Interrupt Priority Vector Status/Clear Register IntpriInterrupt Status/Clear Register Intstatclr InstatInterrupt Pointer Register Intptr Field Descriptions Interrupt Pending/Set Register IntpendsetInterrupt Pointer Register Intptr IntsetTxadrmap Transmit Address Map Register XAMAddress Map Register XAM Field Descriptions RXADRSIZE1 Receive Address Map Size 1 Register RAMS1Receive Address Map Offset 1 Register RAMO1 RXADROFFSET1RXADRSIZE2 Receive Address Map Size 2 Register RAMS2Receive Address Map Offset 2 Register RAMO2 RXADROFFSET2RXADRSIZE3 Receive Address Map Size 3 Register RAMS3Receive Address Map Offset 3 Register RAMO3 RXADROFFSET3RXADRSIZE4 Receive Address Map Size 4 Register RAMS4Receive Address Map Offset 4 Register RAMO4 RXADROFFSET4Chip Version Register Chipver Field Descriptions Chip Version Register ChipverAuto Negotiation Register Autngo Auto Negotiation Register Autngo Field DescriptionsRemote Configuration Registers Vlynq Port Remote Controller RegistersSupported Ordered Sets Appendix a Vlynq Protocol SpecificationsSpecial 8b/10b Code Groups Table A-1. Special 8b/10b Code GroupsFigure A-1. Packet Format 10-bit Symbol Representation Vlynq 2.0 Packet FormatField Value Description Vlynq 2.X Packets Vlynq 2.X Packets Appendix B Write/Read Performance Write PerformanceBurst Size Interface Running at 76.5 MHZ Table B-1. Scaling FactorsBurst Size in 32-bit words Data Bytes Bit Words Mbits/sec Mbytes/secRead Performance Table B-3. Relative Performance with Various LatenciesAdditions/Modifications/Deletions Appendix C Revision HistoryTable C-1. Document Revision History Rfid Products ApplicationsDSP

3.1Revision Register (REVID)

Figure 9. Revision Register (REVID)

REVMAJ

REVMIN

Table 7. Revision Register (REVID) Field Descriptions

Bit

Field

Value

Description

REVMAJ